OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_byte_ctrl.vhd] - Diff between revs 38 and 47

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 38 Rev 47
Line 35... Line 35...
----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_byte_ctrl.vhd,v 1.4 2003-08-09 07:01:13 rherveille Exp $
--  $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $
--
--
--  $Date: 2003-08-09 07:01:13 $
--  $Date: 2004-02-18 11:41:48 $
--  $Revision: 1.4 $
--  $Revision: 1.5 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.4  2003/08/09 07:01:13  rherveille
 
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
 
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
 
--
--               Revision 1.3  2002/12/26 16:05:47  rherveille
--               Revision 1.3  2002/12/26 16:05:47  rherveille
--               Core is now a Multimaster I2C controller.
--               Core is now a Multimaster I2C controller.
--
--
--               Revision 1.2  2002/11/30 22:24:37  rherveille
--               Revision 1.2  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--               Cleaned up code
Line 269... Line 273...
                             c_state  <= st_write;
                             c_state  <= st_write;
                             core_cmd <= I2C_CMD_WRITE;
                             core_cmd <= I2C_CMD_WRITE;
                           else -- stop
                           else -- stop
                             c_state  <= st_stop;
                             c_state  <= st_stop;
                             core_cmd <= I2C_CMD_STOP;
                             core_cmd <= I2C_CMD_STOP;
                             host_ack <= '1'; -- generate acknowledge signal
 
                           end if;
                           end if;
 
 
                           ld <= '1';
                           ld <= '1';
                         end if;
                         end if;
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.