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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_top.vhd] - Diff between revs 15 and 16

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Rev 15 Rev 16
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----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_top.vhd,v 1.1 2001-11-05 12:02:33 rherveille Exp $
--  $Id: i2c_master_top.vhd,v 1.2 2001-11-10 10:52:44 rherveille Exp $
--
--
--  $Date: 2001-11-05 12:02:33 $
--  $Date: 2001-11-10 10:52:44 $
--  $Revision: 1.1 $
--  $Revision: 1.2 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
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        -- registers block
        -- registers block
        regs_block: process(rst_i, wb_clk_i)
        regs_block: process(rst_i, wb_clk_i)
        begin
        begin
                if (rst_i = '0') then
                if (rst_i = '0') then
                        prer <= (others => '0') after Tcq;
                        prer <= (others => '1') after Tcq;
                        ctr  <= (others => '0') after Tcq;
                        ctr  <= (others => '0') after Tcq;
                        txr  <= (others => '0') after Tcq;
                        txr  <= (others => '0') after Tcq;
                        cr   <= (others => '0') after Tcq;
                        cr   <= (others => '0') after Tcq;
                elsif (wb_clk_i'event and wb_clk_i = '1') then
                elsif (wb_clk_i'event and wb_clk_i = '1') then
                        if (wb_rst_i = '1') then
                        if (wb_rst_i = '1') then
                                prer <= (others => '0') after Tcq;
                                prer <= (others => '1') after Tcq;
                                ctr  <= (others => '0') after Tcq;
                                ctr  <= (others => '0') after Tcq;
                                txr  <= (others => '0') after Tcq;
                                txr  <= (others => '0') after Tcq;
                                cr   <= (others => '0') after Tcq;
                                cr   <= (others => '0') after Tcq;
                        else
                        else
                                if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
                                if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
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        end block;
        end block;
 
 
end architecture structural;
end architecture structural;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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