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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_top.vhd,v 1.2 2001-11-10 10:52:44 rherveille Exp $
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-- $Id: i2c_master_top.vhd,v 1.3 2002-11-30 22:24:37 rherveille Exp $
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--
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--
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-- $Date: 2001-11-10 10:52:44 $
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-- $Date: 2002-11-30 22:24:37 $
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-- $Revision: 1.2 $
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-- $Revision: 1.3 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2001/11/10 10:52:44 rherveille
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-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity i2c_master_top is
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entity i2c_master_top is
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generic(
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generic(
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ARST_LVL : std_logic := '0'; -- asynchronous reset level
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ARST_LVL : std_logic := '0' -- asynchronous reset level
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-- Register timing parameters.
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-- Last parameters in list for
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-- verilog compatibility
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Tcq : time := 1 ns -- Clock to output delay
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);
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);
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port (
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port (
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-- wishbone signals
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-- wishbone signals
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wb_clk_i : in std_logic; -- master clock input
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wb_clk_i : in std_logic; -- master clock input
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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| Line 86... |
Line 84... |
);
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);
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end entity i2c_master_top;
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end entity i2c_master_top;
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architecture structural of i2c_master_top is
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architecture structural of i2c_master_top is
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component i2c_master_byte_ctrl is
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component i2c_master_byte_ctrl is
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generic(
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Tcq : time := Tcq
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
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nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
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ena : in std_logic; -- core enable signal
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ena : in std_logic; -- core enable signal
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Line 127... |
signal sr : std_logic_vector(7 downto 0); -- status register
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signal sr : std_logic_vector(7 downto 0); -- status register
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-- internal reset signal
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-- internal reset signal
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signal rst_i : std_logic;
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signal rst_i : std_logic;
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-- internal acknowledge signal
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signal iack_o : std_logic;
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-- done signal: command completed, clear command register
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-- done signal: command completed, clear command register
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signal done : std_logic;
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signal done : std_logic;
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-- command register signals
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-- command register signals
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signal sta, sto, rd, wr, ack, iack : std_logic;
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signal sta, sto, rd, wr, ack, iack : std_logic;
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Line 151... |
begin
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begin
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-- generate internal reset signal
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-- generate internal reset signal
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rst_i <= arst_i xor ARST_LVL;
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rst_i <= arst_i xor ARST_LVL;
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-- generate acknowledge output signal
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-- generate acknowledge output signal
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wb_ack_o <= wb_cyc_i and wb_stb_i; -- because timing is always honored
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gen_ack_o : process(wb_clk_i)
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-- assign wb_dat_o
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assign_dato : process(wb_adr_i, prer, ctr, txr, cr, rxr, sr)
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begin
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begin
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case wb_adr_i is
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if (wb_clk_i'event and wb_clk_i = '1') then
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when "000" =>
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iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
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wb_dat_o <= std_logic_vector(prer( 7 downto 0));
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end if;
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end process gen_ack_o;
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when "001" =>
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wb_dat_o <= std_logic_vector(prer(15 downto 8));
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when "010" =>
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wb_ack_o <= iack_o;
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wb_dat_o <= ctr;
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when "011" =>
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wb_dat_o <= rxr; -- write is transmit register TxR
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when "100" =>
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-- assign wb_dat_o
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wb_dat_o <= sr; -- write is command register CR
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assign_dato : process(wb_clk_i)
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begin
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if (wb_clk_i'event and wb_clk_i = '1') then
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case wb_adr_i is
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when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
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when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
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when "010" => wb_dat_o <= ctr;
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when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
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when "100" => wb_dat_o <= sr; -- write is command register CR
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-- Debugging registers:
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-- Debugging registers:
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-- These registers are not documented.
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-- These registers are not documented.
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-- Functionality could change in future releases
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-- Functionality could change in future releases
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when "101" => wb_dat_o <= txr;
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when "101" =>
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when "110" => wb_dat_o <= cr;
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wb_dat_o <= txr;
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when "111" => wb_dat_o <= (others => '0');
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when others => wb_dat_o <= (others => 'X'); -- for simulation only
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when "110" =>
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wb_dat_o <= cr;
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when "111" =>
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wb_dat_o <= (others => '0');
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when others =>
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wb_dat_o <= (others => 'X'); -- for simulation only
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end case;
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end case;
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end if;
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end process assign_dato;
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end process assign_dato;
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-- registers block
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-- registers block
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regs_block: process(rst_i, wb_clk_i)
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regs_block: process(rst_i, wb_clk_i)
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begin
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begin
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if (rst_i = '0') then
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if (rst_i = '0') then
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prer <= (others => '1') after Tcq;
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prer <= (others => '1');
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ctr <= (others => '0') after Tcq;
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ctr <= (others => '0');
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txr <= (others => '0') after Tcq;
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txr <= (others => '0');
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cr <= (others => '0') after Tcq;
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cr <= (others => '0');
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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if (wb_rst_i = '1') then
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prer <= (others => '1') after Tcq;
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prer <= (others => '1');
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ctr <= (others => '0') after Tcq;
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ctr <= (others => '0');
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txr <= (others => '0') after Tcq;
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txr <= (others => '0');
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cr <= (others => '0') after Tcq;
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cr <= (others => '0');
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else
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else
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if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
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if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
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if (wb_adr_i(2) = '0') then
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if (wb_adr_i(2) = '0') then
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case wb_adr_i(1 downto 0) is
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case wb_adr_i(1 downto 0) is
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when "00" => prer( 7 downto 0) <= unsigned(wb_dat_i) after Tcq;
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when "00" => prer( 7 downto 0) <= unsigned(wb_dat_i);
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when "01" => prer(15 downto 8) <= unsigned(wb_dat_i) after Tcq;
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when "01" => prer(15 downto 8) <= unsigned(wb_dat_i);
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when "10" => ctr <= wb_dat_i after Tcq;
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when "10" => ctr <= wb_dat_i;
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when "11" => txr <= wb_dat_i after Tcq;
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when "11" => txr <= wb_dat_i;
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-- illegal cases, for simulation only
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-- illegal cases, for simulation only
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when others =>
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when others =>
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report ("Illegal write address, setting all registers to unknown.");
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report ("Illegal write address, setting all registers to unknown.");
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prer <= (others => 'X');
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prer <= (others => 'X');
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Line 217... |
txr <= (others => 'X');
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txr <= (others => 'X');
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end case;
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end case;
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elsif ( (core_en = '1') and (wb_adr_i(1 downto 0) = 0) ) then
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elsif ( (core_en = '1') and (wb_adr_i(1 downto 0) = 0) ) then
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-- only take new commands when i2c ore enabled
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-- only take new commands when i2c ore enabled
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-- pending commands are finished
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-- pending commands are finished
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cr <= wb_dat_i after Tcq;
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cr <= wb_dat_i;
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end if;
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end if;
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else
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else
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-- clear command bits when done
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-- clear command bits when done
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if (done = '1') then
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if (done = '1') then
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cr(7 downto 4) <= (others => '0') after Tcq;
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cr(7 downto 4) <= (others => '0');
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end if;
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end if;
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-- reserved bits
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-- reserved bits
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cr(2 downto 1) <= (others => '0') after Tcq;
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cr(2 downto 1) <= (others => '0');
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-- clear iack when irq_flag cleared
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-- clear iack when irq_flag cleared
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cr(0) <= cr(0) and irq_flag;
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cr(0) <= cr(0) and irq_flag;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process regs_block;
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end process regs_block;
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-- decode command register
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-- decode command register
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sta <= cr(7);
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sta <= cr(7);
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sto <= cr(6);
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sto <= cr(6);
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rd <= cr(5);
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rd <= cr(5);
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wr <= cr(4);
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wr <= cr(4);
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Line 281... |
begin
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begin
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-- generate status register bits
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-- generate status register bits
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gen_sr_bits: process (wb_clk_i, rst_i)
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gen_sr_bits: process (wb_clk_i, rst_i)
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begin
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begin
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if (rst_i = '0') then
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if (rst_i = '0') then
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rxack <= '0' after Tcq;
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rxack <= '0';
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tip <= '0' after Tcq;
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tip <= '0';
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irq_flag <= '0' after Tcq;
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irq_flag <= '0';
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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if (wb_rst_i = '1') then
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rxack <= '0' after Tcq;
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rxack <= '0';
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tip <= '0' after Tcq;
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tip <= '0';
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irq_flag <= '0' after Tcq;
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irq_flag <= '0';
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else
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else
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rxack <= irxack after Tcq;
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rxack <= irxack;
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tip <= (rd or wr) after Tcq;
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tip <= (rd or wr);
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-- interrupt request flag is always generated
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-- interrupt request flag is always generated
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irq_flag <= (done or irq_flag) and not iack after Tcq;
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irq_flag <= (done or irq_flag) and not iack;
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end if;
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end if;
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end if;
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end if;
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end process gen_sr_bits;
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end process gen_sr_bits;
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-- generate interrupt request signals
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-- generate interrupt request signals
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gen_irq: process (wb_clk_i, rst_i)
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gen_irq: process (wb_clk_i, rst_i)
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begin
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begin
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if (rst_i = '0') then
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if (rst_i = '0') then
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wb_inta_o <= '0' after Tcq;
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wb_inta_o <= '0';
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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if (wb_rst_i = '1') then
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wb_inta_o <= '0' after Tcq;
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wb_inta_o <= '0';
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else
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else
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-- interrupt signal is only generated when IEN (interrupt enable bit) is set
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-- interrupt signal is only generated when IEN (interrupt enable bit) is set
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wb_inta_o <= irq_flag and ien after Tcq;
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wb_inta_o <= irq_flag and ien;
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end if;
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end if;
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end if;
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end if;
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end process gen_irq;
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end process gen_irq;
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-- assign status register bits
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-- assign status register bits
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Line 324... |
sr(0) <= irq_flag;
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sr(0) <= irq_flag;
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end block;
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end block;
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end architecture structural;
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end architecture structural;
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No newline at end of file
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No newline at end of file
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