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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_top.vhd] - Diff between revs 31 and 34
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| Rev 31 |
Rev 34 |
| Line 35... |
Line 35... |
---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_top.vhd,v 1.4 2002-12-26 16:05:47 rherveille Exp $
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-- $Id: i2c_master_top.vhd,v 1.5 2003-02-01 02:03:06 rherveille Exp $
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--
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--
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-- $Date: 2002-12-26 16:05:47 $
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-- $Date: 2003-02-01 02:03:06 $
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-- $Revision: 1.4 $
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-- $Revision: 1.5 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2002/12/26 16:05:47 rherveille
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-- Core is now a Multimaster I2C controller.
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--
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-- Revision 1.3 2002/11/30 22:24:37 rherveille
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-- Revision 1.3 2002/11/30 22:24:37 rherveille
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-- Cleaned up code
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-- Cleaned up code
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--
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--
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-- Revision 1.2 2001/11/10 10:52:44 rherveille
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-- Revision 1.2 2001/11/10 10:52:44 rherveille
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-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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| Line 335... |
Line 338... |
end process gen_irq;
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end process gen_irq;
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-- assign status register bits
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-- assign status register bits
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sr(7) <= rxack;
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sr(7) <= rxack;
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sr(6) <= i2c_busy;
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sr(6) <= i2c_busy;
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sr(5 downto 2) <= (others => '0'); -- reserved
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sr(5) <= al;
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sr(4 downto 2) <= (others => '0'); -- reserved
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sr(1) <= tip;
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sr(1) <= tip;
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sr(0) <= irq_flag;
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sr(0) <= irq_flag;
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end block;
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end block;
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end architecture structural;
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end architecture structural;
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