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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_top.vhd] - Diff between revs 38 and 51

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Rev 38 Rev 51
Line 35... Line 35...
----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_top.vhd,v 1.6 2003-08-09 07:01:13 rherveille Exp $
--  $Id: i2c_master_top.vhd,v 1.7 2004-03-14 10:17:03 rherveille Exp $
--
--
--  $Date: 2003-08-09 07:01:13 $
--  $Date: 2004-03-14 10:17:03 $
--  $Revision: 1.6 $
--  $Revision: 1.7 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.6  2003/08/09 07:01:13  rherveille
 
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
 
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
 
--
--               Revision 1.5  2003/02/01 02:03:06  rherveille
--               Revision 1.5  2003/02/01 02:03:06  rherveille
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
--
--
--               Revision 1.4  2002/12/26 16:05:47  rherveille
--               Revision 1.4  2002/12/26 16:05:47  rherveille
--               Core is now a Multimaster I2C controller.
--               Core is now a Multimaster I2C controller.
Line 217... Line 221...
                case wb_adr_i is
                case wb_adr_i is
                   when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
                   when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
                   when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
                   when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
                   when "010" => ctr               <= wb_dat_i;
                   when "010" => ctr               <= wb_dat_i;
                   when "011" => txr               <= wb_dat_i;
                   when "011" => txr               <= wb_dat_i;
 
                   when "100" => null; --write to CR, avoid executing the others clause
 
 
                   -- illegal cases, for simulation only
                   -- illegal cases, for simulation only
                   when others =>
                   when others =>
                      report ("Illegal write address, setting all registers to unknown.");
                      report ("Illegal write address, setting all registers to unknown.");
                      prer <= (others => 'X');
                      prer <= (others => 'X');

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