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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_top.vhd,v 1.7 2004-03-14 10:17:03 rherveille Exp $
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-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
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--
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--
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-- $Date: 2004-03-14 10:17:03 $
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-- $Date: 2009-01-20 10:38:45 $
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-- $Revision: 1.7 $
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-- $Revision: 1.8 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.7 2004/03/14 10:17:03 rherveille
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-- Fixed simulation issue when writing to CR register
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--
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-- Revision 1.6 2003/08/09 07:01:13 rherveille
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-- Revision 1.6 2003/08/09 07:01:13 rherveille
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-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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-- Fixed a potential bug in the byte controller's host-acknowledge generation.
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-- Fixed a potential bug in the byte controller's host-acknowledge generation.
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--
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--
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-- Revision 1.5 2003/02/01 02:03:06 rherveille
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-- Revision 1.5 2003/02/01 02:03:06 rherveille
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| Line 76... |
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port (
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port (
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-- wishbone signals
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-- wishbone signals
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wb_clk_i : in std_logic; -- master clock input
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wb_clk_i : in std_logic; -- master clock input
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
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arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
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wb_adr_i : in unsigned(2 downto 0); -- lower address bits
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wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
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wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
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wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
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wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
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wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
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wb_we_i : in std_logic; -- Write enable input
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wb_we_i : in std_logic; -- Write enable input
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wb_stb_i : in std_logic; -- Strobe signals / core select signal
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wb_stb_i : in std_logic; -- Strobe signals / core select signal
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wb_cyc_i : in std_logic; -- Valid bus cycle input
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wb_cyc_i : in std_logic; -- Valid bus cycle input
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| Line 244... |
Line 247... |
cr <= (others => '0');
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cr <= (others => '0');
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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if (wb_rst_i = '1') then
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cr <= (others => '0');
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cr <= (others => '0');
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elsif (wb_wacc = '1') then
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elsif (wb_wacc = '1') then
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if ( (core_en = '1') and (wb_adr_i = 4) ) then
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if ( (core_en = '1') and (wb_adr_i = "100") ) then
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-- only take new commands when i2c core enabled
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-- only take new commands when i2c core enabled
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-- pending commands are finished
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-- pending commands are finished
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cr <= wb_dat_i;
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cr <= wb_dat_i;
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end if;
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end if;
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else
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else
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