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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- Revision 1.7 2004/03/14 10:17:03 rherveille
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-- Revision 1.7 2004/03/14 10:17:03 rherveille
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-- Fixed simulation issue when writing to CR register
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-- Fixed simulation issue when writing to CR register
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--
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--
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-- Revision 1.6 2003/08/09 07:01:13 rherveille
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-- Revision 1.6 2003/08/09 07:01:13 rherveille
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-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity i2c_master_top is
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entity i2c_master_top is
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generic(
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generic(
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ARST_LVL : std_logic := '0' -- asynchronous reset level
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ARST_LVL : std_logic := '0' -- asynchronous reset level
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);
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);
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iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
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iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
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end if;
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end if;
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end process gen_ack_o;
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end process gen_ack_o;
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wb_ack_o <= iack_o;
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wb_ack_o <= iack_o;
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-- generate wishbone write access signal
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-- generate wishbone write access signal
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wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
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wb_wacc <= wb_we_i and iack_o;
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-- assign wb_dat_o
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-- assign wb_dat_o
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assign_dato : process(wb_clk_i)
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assign_dato : process(wb_clk_i)
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begin
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begin
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if (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_clk_i'event and wb_clk_i = '1') then
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-- decode control register
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-- decode control register
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core_en <= ctr(7);
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core_en <= ctr(7);
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ien <= ctr(6);
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ien <= ctr(6);
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-- hookup byte controller block
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-- hookup byte controller block
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byte_ctrl: i2c_master_byte_ctrl port map (
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byte_ctrl: i2c_master_byte_ctrl
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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nReset => rst_i,
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nReset => rst_i,
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ena => core_en,
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ena => core_en,
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clk_cnt => prer,
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clk_cnt => prer,
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