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// --------------------------------------------------------------------
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//////////////////////////////////////////////////////////////////////
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//
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//// ////
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// --------------------------------------------------------------------
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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// i2c_to_wb_top
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// i2c_to_wb_top
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wire i2c_data_out;
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wire i2c_data_out;
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wire i2c_clk_out;
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wire i2c_clk_out;
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wire i2c_data_oe;
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wire i2c_data_oe;
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wire i2c_clk_oe;
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wire i2c_clk_oe;
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wire [31:0] wb_data_i = 32'ha5a5a5a5;
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// wire [31:0] wb_data_i = 32'hd4c3b2a1;
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wire [31:0] wb_data_i;
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wire [31:0] wb_data_o;
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wire [31:0] wb_data_o;
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wire [31:0] wb_addr_o;
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wire [31:0] wb_addr_o;
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wire [3:0] wb_sel_o;
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wire [3:0] wb_sel_o;
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wire wb_we_o;
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wire wb_we_o;
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wire wb_cyc_o;
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wire wb_cyc_o;
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wire wb_stb_o;
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wire wb_stb_o;
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wire wb_ack_i = 1'b1;
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// wire wb_ack_i = 1'b1;
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wire wb_err_i = 1'b0;
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// wire wb_err_i = 1'b0;
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wire wb_rty_i = 1'b0;
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// wire wb_rty_i = 1'b0;
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wire wb_ack_i;
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wire wb_err_i;
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wire wb_rty_i;
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// tristate buffers
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// tristate buffers
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assign i2c_data = i2c_data_oe ? i2c_data_out : 1'bz;
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assign i2c_data = i2c_data_oe ? i2c_data_out : 1'bz;
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assign i2c_clk = i2c_clk_oe ? i2c_clk_out : 1'bz;
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assign i2c_clk = i2c_clk_oe ? i2c_clk_out : 1'bz;
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.i2c_data_out(i2c_data_out),
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.i2c_data_out(i2c_data_out),
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.i2c_clk_out(i2c_clk_out),
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.i2c_clk_out(i2c_clk_out),
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.i2c_data_oe(i2c_data_oe),
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.i2c_data_oe(i2c_data_oe),
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.i2c_clk_oe(i2c_clk_oe),
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.i2c_clk_oe(i2c_clk_oe),
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.thd_dat(4'h8),
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.wb_data_i(wb_data_i),
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.wb_data_i(wb_data_i),
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.wb_data_o(wb_data_o),
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.wb_data_o(wb_data_o),
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.wb_addr_o(wb_addr_o),
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.wb_addr_o(wb_addr_o[7:0]),
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.wb_sel_o(wb_sel_o),
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.wb_sel_o(wb_sel_o),
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.wb_we_o(wb_we_o),
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.wb_we_o(wb_we_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_stb_o(wb_stb_o),
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.wb_stb_o(wb_stb_o),
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.wb_ack_i(wb_ack_i),
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.wb_ack_i(wb_ack_i),
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.wb_rst_i(tb_rst)
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.wb_rst_i(tb_rst)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// wb_slave_model
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wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
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i_wb_slave_model(
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.clk_i(tb_clk),
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.rst_i(tb_rst),
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.dat_o(wb_data_i),
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.dat_i(wb_data_o),
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.adr_i(wb_addr_o),
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.cyc_i(wb_cyc_o),
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.stb_i(wb_stb_o),
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.we_i(wb_we_o),
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.sel_i(wb_sel_o),
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.ack_o(wb_ack_i),
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.err_o(wb_err_i),
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.rty_o(wb_rty_i)
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);
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// --------------------------------------------------------------------
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// glitch_generator
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// glitch_generator
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glitch_generator i_g1( i2c_data );
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glitch_generator i_g1( i2c_data );
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glitch_generator i_g2( i2c_clk );
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glitch_generator i_g2( i2c_clk );
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