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----------------------------------------------------------------------------------
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-- Company: University Rey Juan Carlos I - FRAV Group (www.frav.es)
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-- Engineer: Victor Lopez Lorenzo (galland (at) opencores (dot) org)
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--
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-- Create Date: 17:46:20 12/June/2008
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-- Project Name: I2C16bits to WISHBONE Wrapper
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-- Tool versions: Xilinx ISE 9.2i
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-- Description: WISHBONE wrapper for the "I2C controller core" by Richard Herveille
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-- Fully transparent I2C <-> WISHBONE operation: A WB read/write of address X
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-- becomes an I2C read/write of reg. X and the I2C slave's response is sent back to the WB bus.
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-- This is very useful as the raw control of the I2C controller core is very cumbersome,
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-- requiring many commands to make a single I2C read/write.
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-- IMPORTANT: This core makes I2C operations of 16 bits!
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--
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-- Dependencies: "I2C controller core" by Richard Herveille on OpenCores http://www.opencores.org/projects.cgi/web/i2c
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--
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-- Additional Comments:
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--
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-- This core wraps the OpenCores' "I2C controller core" to virtually convert an I2C slave
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-- into a WISHBONE slave, it does all the necessary I2C core's setup automatically
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-- ONLY THREE CONSTANTS MUST BE CHANGED IN THIS FILE:
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-- 1) Set your I2C slave address constant (SLAVE_ADDR1)
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-- 2) Set the right prescaler constants (PRESCALER_HI and PRESCALER_LO)
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-- according to "I2C controller core" documentation: they depend on
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-- wb_clk_i and the desired I2C SCL frequency with this simple formula:
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-- prescale = (wb_clk_i /(5*desired SCL)) - 1
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-- Examples:
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-- wb_clk_i = 48 MHz, desired SCL = 384 KHz -> PRESCALER_HI = 00h and PRESCALER_LO = 18h (24)
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-- wb_clk_i = 33 MHz, desired SCL = 100 KHz -> PRESCALER_HI = 00h and PRESCALER_LO = 40h (64)
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--
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--
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--
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-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1
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-- That is you may use it in ANY project (commercial or not) without paying me a cent.
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-- You are only required to include in the copyrights/about section of accompanying
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-- software and manuals of use that your system contains a "I2CWB Wrapper
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-- (C) Victor Lopez Lorenzo under LGPL license"
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-- This holds also in the case where you modify the core, as the resulting core
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-- would be a derived work.
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-- Also, for the sake of gratefulness, I would like to know if you use this core
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-- in a project of yours, just an email will do ;)
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--
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-- Please take good note of the disclaimer section of the LPGL license, as I don't
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-- take any responsability for anything that this core does.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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entity I2C16bits_wrapper is port (
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wb_clk_i : in std_logic; -- master clock input
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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--WB slave
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i2c16_wb_adr_i : in std_logic_vector(7 downto 0); -- I2C reg number
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i2c16_wb_dat_i : in std_logic_vector(15 downto 0); -- I2C data to write
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i2c16_wb_dat_o : out std_logic_vector(15 downto 0); -- I2C data read
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i2c16_wb_we_i : in std_logic; -- Write enable input
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i2c16_wb_stb_i : in std_logic; -- Strobe signals / core select signal
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i2c16_wb_cyc_i : in std_logic; -- Valid bus cycle input
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i2c16_wb_ack_o : out std_logic; -- Bus cycle acknowledge output
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i2c16_wb_err_o : out std_logic; -- Bus cycle error output
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-- i2c lines
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scl_pad_i : in std_logic; -- i2c clock line input
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scl_pad_o : out std_logic; -- i2c clock line output
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scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
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sda_pad_i : in std_logic; -- i2c data line input
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sda_pad_o : out std_logic; -- i2c data line output
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sda_padoen_o : out std_logic); -- i2c data line output enable, active low
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end I2C16bits_wrapper;
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architecture Behavioral of I2C16bits_wrapper is
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--higher 8 bits of prescaler for I2C master core (reg 0x01)
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constant PRESCALER_HI : std_logic_vector(7 downto 0) := x"00";
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--lower 8 bits of prescaler for I2C master core (reg 0x00):
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constant PRESCALER_LO : std_logic_vector(7 downto 0) := x"40";
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--7 bit address of I2C slave
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constant SLAVE_ADDR1 : std_logic_vector(6 downto 0) := "1001000";
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--I2C master core registers
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constant PRERlo : unsigned(2 downto 0) := "000";
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constant PRERhi : unsigned(2 downto 0) := "001";
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constant CTR : unsigned(2 downto 0) := "010";
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constant TXR : unsigned(2 downto 0) := "011";
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constant RXR : unsigned(2 downto 0) := "011";
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constant CR : unsigned(2 downto 0) := "100";
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constant SR : unsigned(2 downto 0) := "100";
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component i2c_master_top
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generic(ARST_LVL : std_logic := '1'); -- asynchronous reset level
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port (
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-- wishbone signals
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wb_clk_i : in std_logic; -- master clock input
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
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wb_adr_i : in unsigned(2 downto 0); -- lower address bits
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wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
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wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
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wb_we_i : in std_logic; -- Write enable input
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wb_stb_i : in std_logic; -- Strobe signals / core select signal
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wb_cyc_i : in std_logic; -- Valid bus cycle input
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wb_ack_o : out std_logic; -- Bus cycle acknowledge output
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wb_inta_o : out std_logic; -- interrupt request output signal
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-- i2c lines
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scl_pad_i : in std_logic; -- i2c clock line input
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scl_pad_o : out std_logic; -- i2c clock line output
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scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
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sda_pad_i : in std_logic; -- i2c data line input
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sda_pad_o : out std_logic; -- i2c data line output
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sda_padoen_o : out std_logic); -- i2c data line output enable, active low
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end component i2c_master_top;
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--Signals for I2C core interface
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signal i2c_wb_adr : unsigned(2 downto 0); -- lower address bits
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signal i2c_wb_dat_i : std_logic_vector(7 downto 0); -- Databus input
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signal i2c_wb_dat_o : std_logic_vector(7 downto 0); -- Databus output
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signal i2c_wb_we : std_logic; -- Write enable input
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signal i2c_wb_stb : std_logic; -- Strobe signals / core select signal
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signal i2c_wb_cyc : std_logic; -- Valid bus cycle input
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signal i2c_wb_ack : std_logic; -- Bus cycle acknowledge output
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signal i2c_wb_inta : std_logic;
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signal SLAVE_ADDR : std_logic_vector(6 downto 0);
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begin
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Wishbone_slave : process (wb_clk_i, wb_rst_i)
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--Initialization of I2C master core (normal WB transfers):
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--write PRESCALER_HI in PRERhi reg (0x01)
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--write PRESCALER_LO in PRERlo reg (0x00)
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--write 80h in CTR reg (0x02) (Enable I2C core and disable interrupts)
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--In parenthesis: I2C master core's Wishbone regs affected (bits to set, or / to clear) TXR and CR imply write, RXR and SR imply read:
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--
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--I2C 16-bit WRITE sequence is:
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--START / send I2C slave address with WRITE bit / wait ACK (TXR, CR(STA&WR), wait SR(/RxACK&/TIP))
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--send I2C slave register to write / wait ACK (TXR, CR(WR), wait SR(/RxACK&/TIP))
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--send high 8 bits of data to write / wait ACK (TXR, CR(WR), wait SR(/RxACK&/TIP))
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--send low 8 bits of data to write / wait ACK / STOP signal (TXR, CR(WR&STO), wait SR(/RxACK&/TIP))
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--
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--I2C 16-bit READ sequence is:
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--START / send I2C slave address with WRITE bit / wait ACK (TXR, CR(STA&WR), wait SR(/RxACK&/TIP))
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--send I2C slave register to read / wait ACK (TXR, CR(WR), wait SR(/RxACK&/TIP))
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--START again / send I2C slave address with READ bit / wait ACK (TXR, CR(STA&WR), wait SR(/RxACK&/TIP))
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--receive high 8 bits of data read / send ACK (CR(RD), wait SR(/RxACK&/TIP), save high data byte from RXR)
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--receive low 8 bits of data read / send NACK / STOP signal (CR(RD&STO&ACK), wait SR(/RxACK&/TIP), save low data byte from RXR)
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--
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variable State : integer range 0 to 31;
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variable Init: integer range 0 to 3;
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variable WaitACK, WaitSR : std_logic;
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variable data : std_logic_vector(7 downto 0);
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begin
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if (wb_rst_i = '1') then
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i2c_wb_adr <= SR;
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i2c_wb_dat_i <= (others => '0');
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i2c_wb_we <= '0';
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i2c_wb_cyc <= '0';
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i2c_wb_stb <= '0';
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i2c16_wb_ack_o <= '0';
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i2c16_wb_err_o <= '0';
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i2c16_wb_dat_o <= (others => '0');
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State := 0;
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Init := 0;
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WaitACK := '0';
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WaitSR := '0'; --used to do a WB block read until RxACK and TIP bits are negated in reg SR
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data := (others => '0');
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SLAVE_ADDR <= SLAVE_ADDR1;
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elsif (wb_clk_i = '1' and wb_clk_i'event) then
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i2c16_wb_ack_o <= '0'; --only up one cycle
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--i2c16_wb_err_o <= '0';
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if (WaitACK = '1') then --stay here until WB ACK is received from I2C master core or until I2C transfer complete (WaitSR)
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if (i2c_wb_ack = '1') then
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if (i2c_wb_adr = SR and i2c_wb_we = '0') then --reading Status register?
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if (i2c_wb_dat_o(5) = '1') then --error?
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i2c16_wb_err_o <= '1';
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else
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i2c16_wb_err_o <= '0';
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end if;
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if (i2c_wb_dat_o(1) = '0') then --transfer finished?
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WaitSR := '0';
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end if;
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end if;
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if (WaitSR = '0') then
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WaitACK := '0';
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data := i2c_wb_dat_o;
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i2c_wb_we <= '0';
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i2c_wb_cyc <= '0';
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i2c_wb_stb <= '0';
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end if;
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end if;
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else
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--defaults unless overriden
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i2c_wb_we <= '1';
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i2c_wb_cyc <= '1';
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i2c_wb_stb <= '1';
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WaitACK := '1';
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WaitSR := '0';
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if (Init /= 3) then --initializing I2C master core
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case Init is
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when 0 => --write prescaler's high byte (0x01)
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i2c_wb_adr <= PRERhi;
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i2c_wb_dat_i <= PRESCALER_HI;
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when 1 => --write prescaler's low byte (0x00)
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i2c_wb_adr <= PRERlo;
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i2c_wb_dat_i <= PRESCALER_LO;
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when others => --2 write CTR reg (0x02)
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i2c_wb_adr <= CTR;
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i2c_wb_dat_i <= x"80";
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end case;
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Init := Init + 1;
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else
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--I2C reg read/write
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if (i2c16_wb_cyc_i = '1' and i2c16_wb_stb_i = '1') then
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case State is
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--COMMON READ AND WRITE
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when 0 => --write to TXR the slave address followed by Write bit ('0')
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i2c_wb_adr <= TXR;
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i2c_wb_dat_i <= SLAVE_ADDR & '0';
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--i2c_wb_dat_i <= i2c16_wb_adr_i(6 downto 0) & '0';
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when 1 => --write WR and STA bits to CR
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i2c_wb_adr <= CR;
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i2c_wb_dat_i <= "10010000";
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when 2 => --wait for SR to negate TIP and RxACK
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i2c_wb_adr <= SR;
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i2c_wb_we <= '0';
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WaitSR := '1';
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when 3 => --write to TXR the I2C register to read/write
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i2c_wb_adr <= TXR;
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i2c_wb_dat_i <= i2c16_wb_adr_i;
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--i2c_wb_dat_i <= x"00";
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when 4 => --write WR bit to CR
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i2c_wb_adr <= CR;
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i2c_wb_dat_i <= "00010000";
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when 5 => --wait for SR to negate TIP and RxACK
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i2c_wb_adr <= SR;
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i2c_wb_we <= '0';
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WaitSR := '1';
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--COMMON STEPS CHANGING ONLY DATA FOR READ OR WRITE
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when 6 => --write to TXR... READS: send I2C slave address with read bit or WRITES: send higher 8 bits of data
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i2c_wb_adr <= TXR;
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if (i2c16_wb_we_i = '1') then
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i2c_wb_dat_i <= i2c16_wb_dat_i(15 downto 8); --write
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else
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i2c_wb_dat_i <= SLAVE_ADDR & '1'; --read
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--i2c_wb_dat_i <= i2c16_wb_adr_i(6 downto 0) & '1';
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end if;
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when 7 => --write to CR... READS: WR and STA bits set or WRITES: WR bit set
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i2c_wb_adr <= CR;
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if (i2c16_wb_we_i = '1') then
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i2c_wb_dat_i <= "00010000"; --write
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else
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i2c_wb_dat_i <= "10010000"; --read
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end if;
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when 8 => --wait for SR to negate TIP and RxACK and change State for next steps according to READ or WRITE
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i2c_wb_adr <= SR;
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i2c_wb_we <= '0';
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WaitSR := '1';
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if (i2c16_wb_we_i = '0') then
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State := 12; --read (go to following read state minus 1, because it will be incremented after this case)
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end if;
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--WRITE: send the lower 8 bits of data
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when 9 => --write to TXR the lower 8 bits of data
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i2c_wb_adr <= TXR;
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i2c_wb_dat_i <= i2c16_wb_dat_i(7 downto 0);
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when 10 => --write to CR with WR and STO bits set
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i2c_wb_adr <= CR;
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i2c_wb_dat_i <= "01010000"; --WR and STO bits
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when 11 => --wait for SR to negate TIP and RxACK
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i2c_wb_adr <= SR;
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i2c_wb_we <= '0';
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WaitSR := '1';
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when 12 => --rise I2C16_ACK to mark operation finished
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i2c16_wb_ack_o <= '1';
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i2c16_wb_dat_o <= i2c16_wb_dat_i;
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WaitACK := '0'; --override defaults
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i2c_wb_cyc <= '0';
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i2c_wb_stb <= '0';
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i2c_wb_we <= '0';
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State := 31; --go to idle state
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--READ: receive the 16 bits of data
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when 13 => --write in CR the RD bit set
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i2c_wb_adr <= CR;
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i2c_wb_dat_i <= "00100000"; --RD
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when 14 => --wait for SR to negate TIP and RxACK
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i2c_wb_adr <= SR;
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i2c_wb_we <= '0';
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WaitSR := '1';
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when 15 => --read high data byte from RXR
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i2c_wb_adr <= RXR;
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i2c_wb_we <= '0';
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when 16 => --save high data byte and write in CR with the RD, STO and ACK bits set (ACK set=NACK)
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i2c16_wb_dat_o(15 downto 8) <= data;
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i2c_wb_adr <= CR;
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i2c_wb_dat_i <= "01101000"; --RD,STO,ACK
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when 17 => --wait for SR to negate TIP and RxACK
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i2c_wb_adr <= SR;
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i2c_wb_we <= '0';
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WaitSR := '1';
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when 18 => --read low data byte from RXR
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i2c_wb_adr <= RXR;
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i2c_wb_we <= '0';
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when 19 => --save low data byte and write in CR to clear ACK bit
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i2c16_wb_dat_o(7 downto 0) <= data;
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i2c_wb_adr <= CR;
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i2c_wb_dat_i <= "00000000"; --because the ACK/NACK bit is not autocleared by I2C master core
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when 20 => --rise I2C16_ACK to mark operation finished
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i2c16_wb_ack_o <= '1';
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WaitACK := '0'; --override defaults
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i2c_wb_cyc <= '0';
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i2c_wb_stb <= '0';
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i2c_wb_we <= '0';
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State := 31; --go to idle state
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--IDLE STATE
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when others => --31
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--operation finished: stay here until i2c16_cyc and i2c16_stb go down so State resets itself to 0
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i2c_wb_cyc <= '0';
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i2c_wb_stb <= '0';
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i2c_wb_we <= '0';
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SLAVE_ADDR <= SLAVE_ADDR1;
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WaitACK := '0';
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end case;
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if (State /= 31) then State := State + 1; end if;
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else
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State := 0;
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i2c16_wb_dat_o <= (others => '0');
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--override defaults:
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i2c_wb_cyc <= '0';
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i2c_wb_stb <= '0';
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i2c_wb_we <= '0';
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WaitACK := '0';
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end if;
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end if;
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end if;
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end if;
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end process Wishbone_slave;
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----------------------------
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-- I2C Master Core
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----------------------------
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I2CM : i2c_master_top
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generic map ('1')
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port map (
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wb_clk_i => wb_clk_i, -- master clock input
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wb_rst_i => wb_rst_i, -- synchronous active high reset
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arst_i => '0', -- asynchronous reset
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wb_adr_i => i2c_wb_adr, -- lower address bits
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wb_dat_i => i2c_wb_dat_i, -- Databus input
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wb_dat_o => i2c_wb_dat_o, -- Databus output
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wb_we_i => i2c_wb_we, -- Write enable input
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wb_stb_i => i2c_wb_stb, -- Strobe signals / core select signal
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wb_cyc_i => i2c_wb_cyc, -- Valid bus cycle input
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wb_ack_o => i2c_wb_ack, -- Bus cycle acknowledge output
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wb_inta_o => i2c_wb_inta, -- interrupt request output signal
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scl_pad_i => scl_pad_i, -- i2c clock line input
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scl_pad_o => scl_pad_o, -- i2c clock line output
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scl_padoen_o => scl_padoen_o, -- i2c clock line output enable, active low
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sda_pad_i => sda_pad_i, -- i2c data line input
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sda_pad_o => sda_pad_o, -- i2c data line output
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sda_padoen_o => sda_padoen_o); -- i2c data line output enable, active low
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end Behavioral;
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