| Line 44... |
Line 44... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/08/07 12:33:29 gedra
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-- De-linted.
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--
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-- Revision 1.1 2004/08/04 14:31:02 gedra
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-- Revision 1.1 2004/08/04 14:31:02 gedra
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-- Top level test bench.
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-- Top level test bench.
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--
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--
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--
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--
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--
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--
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| Line 352... |
Line 355... |
wb_write_32(TX2_CONFIG, 16#00140703#); -- 20bit resolution
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wb_write_32(TX2_CONFIG, 16#00140703#); -- 20bit resolution
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message("Enable recevier 2:");
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message("Enable recevier 2:");
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wb_write_32(RX2_INTMASK, 16#00000003#); -- enable interrupts
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wb_write_32(RX2_INTMASK, 16#00000003#); -- enable interrupts
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wb_write_32(RX2_CONFIG, 16#00180003#); -- 24bit resolution
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wb_write_32(RX2_CONFIG, 16#00180003#); -- 24bit resolution
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wait_for_event("Wait for transmitter 2 LSBF interrupt", 150 us, tx2_int_o);
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wait_for_event("Wait for transmitter 2 LSBF interrupt", 150 us, tx2_int_o);
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wait_for_event("Wait for recevier 2 LSBF interrupt", 150 us, rx2_int_o);
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wait for 1 us;
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message("Check for receiver LSBF interrupt:");
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wb_check_32(RX2_INTSTAT, 16#00000001#);
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message("Clear transmitter LSBF interrupt:");
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message("Clear transmitter LSBF interrupt:");
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wb_write_32(TX2_INTSTAT, 16#00000001#);
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wb_write_32(TX2_INTSTAT, 16#00000001#);
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wb_check_32(TX2_INTSTAT, 16#00000000#);
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wb_check_32(TX2_INTSTAT, 16#00000000#);
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signal_check("tx2_int_o", '0', tx2_int_o);
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signal_check("tx2_int_o", '0', tx2_int_o);
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message("Clear receiver LSBF interrupt:");
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message("Clear receiver LSBF interrupt:");
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| Line 371... |
Line 376... |
CHKL: for i in 0 to 7 - idx loop
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CHKL: for i in 0 to 7 - idx loop
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wb_check_32(RX2_BUF_BASE + 2*i, (32767 - (i+idx)*497)*256);
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wb_check_32(RX2_BUF_BASE + 2*i, (32767 - (i+idx)*497)*256);
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wb_check_32(RX2_BUF_BASE + 2*i + 1, (32768 + (i+idx)*497)*256);
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wb_check_32(RX2_BUF_BASE + 2*i + 1, (32768 + (i+idx)*497)*256);
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end loop;
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end loop;
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wait_for_event("Wait for transmitter 2 HSBF interrupt", 150 us, tx2_int_o);
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wait_for_event("Wait for transmitter 2 HSBF interrupt", 150 us, tx2_int_o);
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wait_for_event("Wait for recevier 2 HSBF interrupt", 150 us, rx2_int_o);
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wait for 1 us;
|
|
message("Check for receiver LSBF interrupt:");
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wb_check_32(RX2_INTSTAT, 16#00000002#);
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message("Clear transmitter HSBF interrupt:");
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message("Clear transmitter HSBF interrupt:");
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wb_write_32(TX2_INTSTAT, 16#00000002#);
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wb_write_32(TX2_INTSTAT, 16#00000002#);
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wb_check_32(TX2_INTSTAT, 16#00000000#);
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wb_check_32(TX2_INTSTAT, 16#00000000#);
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signal_check("tx2_int_o", '0', tx2_int_o);
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signal_check("tx2_int_o", '0', tx2_int_o);
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message("Clear receiver HSBF interrupt:");
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message("Clear receiver HSBF interrupt:");
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