| Line 41... |
Line 41... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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|
-- Revision 1.2 2004/08/06 18:55:43 gedra
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-- De-linting.
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--
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-- Revision 1.1 2004/08/03 18:50:29 gedra
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-- Revision 1.1 2004/08/03 18:50:29 gedra
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-- Receiver Wishbone cycle decoder.
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-- Receiver Wishbone cycle decoder.
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--
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--
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--
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--
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--
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--
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| Line 192... |
Line 195... |
end process SMA;
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end process SMA;
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-- read and write strobe generation
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-- read and write strobe generation
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version_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXVERSION and ird = '1'
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version_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXVERSION and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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config_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and ird = '1'
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config_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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config_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and iwr = '1'
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config_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXCONFIG and iwr = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and ird = '1'
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intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and iwr = '1'
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intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTMASK and iwr = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and ird = '1'
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intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and iwr = '1'
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intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_RXINTSTAT and iwr = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
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mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
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|
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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