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[/] [i2s_interface/] [trunk/] [rtl/] [vhdl/] [tx_i2s_pack.vhd] - Diff between revs 11 and 18
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/08/04 14:29:10 gedra
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-- Transmitter component declarations.
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--
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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port (
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port (
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wb_clk_i: in std_logic; -- wishbone clock
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wb_clk_i: in std_logic; -- wishbone clock
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conf_res: in std_logic_vector(5 downto 0); -- sample resolution
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conf_res: in std_logic_vector(5 downto 0); -- sample resolution
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conf_ratio: in std_logic_vector(7 downto 0); -- clock divider ratio
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conf_ratio: in std_logic_vector(7 downto 0); -- clock divider ratio
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conf_swap: in std_logic; -- left/right sample order
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conf_swap: in std_logic; -- left/right sample order
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conf_inten: in std_logic; -- interrupt enable
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conf_en: in std_logic; -- transmitter/recevier enable
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conf_en: in std_logic; -- transmitter/recevier enable
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i2s_sd_i: in std_logic; -- I2S serial data input
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i2s_sd_i: in std_logic; -- I2S serial data input
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i2s_sck_i: in std_logic; -- I2S clock input
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i2s_sck_i: in std_logic; -- I2S clock input
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i2s_ws_i: in std_logic; -- I2S word select input
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i2s_ws_i: in std_logic; -- I2S word select input
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sample_dat_i: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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sample_dat_i: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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