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[/] [i2s_interface/] [trunk/] [rtl/] [vhdl/] [tx_i2s_tops.vhd] - Diff between revs 15 and 18

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Rev 15 Rev 18
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-- Revision 1.1  2004/08/04 14:30:28  gedra
 
-- Transmitter top level, slave mode.
 
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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
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  signal config_rd, config_wr, status_rd : std_logic;
  signal config_rd, config_wr, status_rd : std_logic;
  signal config_dout, status_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal config_dout, status_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal intmask_bits, intmask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal intmask_bits, intmask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal intmask_rd, intmask_wr: std_logic;
  signal intmask_rd, intmask_wr: std_logic;
  signal intstat_dout, intstat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal intstat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal intstat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal intstat_rd, intstat_wr : std_logic;
  signal intstat_rd, intstat_wr : std_logic;
  signal evt_hsbf, evt_lsbf : std_logic;
  signal evt_hsbf, evt_lsbf : std_logic;
  signal mem_wr, mem_rd: std_logic;
  signal mem_wr, mem_rd: std_logic;
  signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
  signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
  signal sample_data: std_logic_vector(DATA_WIDTH - 1 downto 0);
  signal sample_data: std_logic_vector(DATA_WIDTH - 1 downto 0);
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    port map (
    port map (
      wb_clk_i => wb_clk_i,
      wb_clk_i => wb_clk_i,
      conf_res => conf_res,
      conf_res => conf_res,
      conf_ratio => conf_ratio,
      conf_ratio => conf_ratio,
      conf_swap => conf_tswap,
      conf_swap => conf_tswap,
      conf_inten => conf_tinten,
 
      conf_en => conf_txen,
      conf_en => conf_txen,
      i2s_sd_i => zero,
      i2s_sd_i => zero,
      i2s_sck_i => i2s_sck_i,
      i2s_sck_i => i2s_sck_i,
      i2s_ws_i => i2s_ws_i,
      i2s_ws_i => i2s_ws_i,
      sample_dat_i => sample_data,
      sample_dat_i => sample_data,

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