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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity AnalogBusPorts is
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port (
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SClk : in std_logic; --this whole schebang runs of the analog serial bus clock
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LRClk : in std_logic; --which channel at the moment?
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AdcData : in std_logic; --data coming in from adc
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DacData : out std_logic; --
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SampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
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nSampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
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LastAdcSample : out std_logic_vector(23 downto 0); --buffer for fifo data
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NextDacSample : in std_logic_vector(23 downto 0)--; --buffer for fifo data
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);
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end AnalogBusPorts;
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architecture AnalogBus of AnalogBusPorts is
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signal LastLRClk : std_logic; --to keep track of edges
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--sample buffers
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signal CurrentAdcSample : std_logic_vector(23 downto 0);
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signal CurrentDacSample : std_logic_vector(23 downto 0);
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signal AdcBitIndex : std_logic_vector(5 downto 0);
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signal DacBitIndex : std_logic_vector(5 downto 0);
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begin
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process (SClk)
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begin
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if (SClk'event and SClk = '1') then
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--move to next bit on each clock of the serial
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AdcBitIndex <= AdcBitIndex + "000001";
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DacBitIndex <= DacBitIndex + "000001";
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--Just moved to the MSB of the other channel
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if ( LRClk = (not(LastLRClk)) ) then
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LastLRClk <= LRClk; --reset for next edge
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if (LRClk = '1') then
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AdcBitIndex <= "000000"; --reset at MSB of sample
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DacBitIndex <= "000001"; --reset at MSB of sample
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end if;
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end if;
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end if;
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if (SClk'event and SClk = '0') then
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--if we just finished a sample, better stick it in the adc fifo
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--Left ADC Channel
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if ( (AdcBitIndex = "111100") ) then --idx=60, which is in the middle of the 8 unused clocks for the R channel.
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LastAdcSample <= CurrentAdcSample(23 downto 0);
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CurrentDacSample(23 downto 0) <= NextDacSample;
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end if;
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--Right ADC Channel
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if ( (AdcBitIndex = "011100") ) then --idx=28, which is in the middle of the 8 unused clocks for the L channel.
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LastAdcSample <= CurrentAdcSample(23 downto 0);
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CurrentDacSample(23 downto 0) <= NextDacSample;
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end if;
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if ( (AdcBitIndex = "000000") ) then
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SampleStrobe <= '1';
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nSampleStrobe <= '0';
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end if;
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if ( (AdcBitIndex = "100000") ) then
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SampleStrobe <= '0'; --50% duty approx
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nSampleStrobe <= '1';
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end if;
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--put each bit into/from the appropriate location in the sample buffer
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if (AdcBitIndex(4 downto 0) < "11000") then --ignore the top 8 MSB's (24 bits of data in 32 bit transaction)
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CurrentAdcSample(Conv_INTEGER(AdcBitIndex(4 downto 0))) <= AdcData;
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end if;
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if (DacBitIndex(4 downto 0) < "11000") then --ignore the top 8 MSB's (24 bits of data in 32 bit transaction)
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DacData <= CurrentDacSample(Conv_INTEGER(DacBitIndex(4 downto 0)));
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end if;
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end if; --if (SClk'event and SClk = '1') then
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end process; --process (SClk)
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end AnalogBus;
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