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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ClocksPorts is
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port (
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Xtal : in std_logic; --main system oscillator
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LRClk : out std_logic; --LR clock for analog serial bus
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SClk : out std_logic; --Serial Bit clock for analog serial bus
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MClk : out std_logic--; --Master clock for analog serial bus (runs DeltaSig hardware in converters)
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);
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end ClocksPorts;
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architecture Clocks of ClocksPorts is
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signal XtalDiv : std_logic_vector(3 downto 0);
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signal div256 : std_logic_vector(8 downto 0);
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begin
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MClk <= div256(0); --run at mclk (XtalDiv/2)
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SClk <= div256(2); --divide MCLK by 4 to Get SCLK (64*Fs)
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LRClk <= div256(8); --divide MCLK by 256 to Get LRCLK (1*Fs)
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process (Xtal)
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begin
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if (Xtal'event and Xtal = '1') then
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--the following divider calculations assume a Xtal input of 25MHz:
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XtalDiv <= XtalDiv + "0001";
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--if (XtalDiv = "1001") then --9: divide by 10 -> fs=4.833kHz
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if (XtalDiv = "0101") then --5: divide by 6 -> fs=8.137kHz
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--if (XtalDiv = "0100") then --4: divide by 5 -> fs=9.766kHz
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--if (XtalDiv = "0011") then --3: divide by 4 -> fs=12kHz
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--if (XtalDiv = "0010") then --2: divide by 3 -> fs=16kHz
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--if (XtalDiv = "0001") then --1: divide by 2 -> fs=32kHz
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--if 'this divider removed : divide by 1 -> fs=48kHz
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--reset master divide counter
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XtalDiv <= "0000";
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--drive other dividers...
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div256 <= div256 + "000000001";
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end if; -- if (XtalDiv = ...
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end if; --if (Xtal'event ...
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end process;
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end Clocks;
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