URL https://opencores.org/ocsvn/i2sparalell/i2sparalell/trunk

Subversion Repositories i2sparalell

[/] [i2sparalell/] [trunk/] [I2SParalell.ucf] - Diff between revs 2 and 3

Rev 2	Rev 3
?rev1line?	?rev2line?
	`# Clock`

	`NET "Xtal" PERIOD = 40; # 40ns = 25MHz`
	`# A/D Fifo Interface`

	`# FIFO CTRL`

	`# ADC/DAC`

	`# EOF`
	`#PACE: Start of Constraints generated by PACE`

	`#PACE: Start of PACE I/O Pin Assignments`
	`NET "AdcData" LOC = "P2" \| PULLUP ; #PullUp for I2S on CS5340; PullDn is LJ mode, which causes 1-bit timing error (volume/2)\| #PullUp for I2S on CS5340; PullDn is LJ mode, which causes 1-bit timing error (volume/2)`
	`NET "ADCSampleBus<0>" LOC = "P18" ; # AvrA7`
	`NET "ADCSampleBus<1>" LOC = "P16" ; # AvrA6`
	`NET "ADCSampleBus<2>" LOC = "P14" ; # AvrA5`
	`NET "ADCSampleBus<3>" LOC = "P13" ; # AvrA4`
	`NET "ADCSampleBus<4>" LOC = "P12" ; # AvrA3`
	`NET "ADCSampleBus<6>" LOC = "P7" ; # AvrA1`
	`NET "DacData" LOC = "P5" ;`
	`NET "DACSampleBus<0>" LOC = "P19" ; # AvrC7`

	`NET "DACSampleBus<1>" LOC = "P20" ; # AvrC6`
	`NET "DACSampleBus<2>" LOC = "P21" ; # AvrC5`
	`NET "DACSampleBus<3>" LOC = "P22" ; # AvrC4`
	`NET "DACSampleBus<4>" LOC = "P23" ; # AvrC3`
	`NET "DACSampleBus<6>" LOC = "P28" ; # AvrC1`
	`NET "LDataStrobe" LOC = "P40" ; # alias e5`
	`NET "LRClk" LOC = "P42" ;`
	`NET "MClk" LOC = "P3" ;`
	`NET "nDebugLoopBack" LOC = "P30" \| PULLUP ;`
	`NET "RDataStrobe" LOC = "P41" ; # alias e4`

	`NET "SClk" LOC = "P4" ;`
	`NET "Xtal" LOC = "P43" ; # Clock input - GCLK0`


	`#PACE: Start of PACE Area Constraints`

	`#PACE: Start of PACE Prohibit Constraints`

	`#PACE: End of Constraints generated by PACE`