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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--This has been tested on a Xilinx XC2C256 (Coolrunner-II 256) with
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-- Cirrus CS5340 ADC's and CS4334 DAC's connected to an Atmel AVR AtMega128L uC.
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entity I2SParalellPorts is
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port (
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Xtal : in std_logic;
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--analog bus ports
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AdcData : in std_logic;
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DacData : out std_logic;
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LRClk : out std_logic;
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SClk : out std_logic;
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MClk : out std_logic;
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--digital bus ports
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ADCSampleBus : out std_logic_vector(23 downto 0);
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DACSampleBus : in std_logic_vector(23 downto 0);
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LDataStrobe : out std_logic;
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RDataStrobe : out std_logic;
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--debug port
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nDebugLoopBack : in std_logic --;
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);
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end I2SParalellPorts;
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architecture I2SParalell of I2SParalellPorts is
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component ClocksPorts
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port (
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Xtal : in std_logic; --main system oscillator
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LRClk : out std_logic; --LR clock for analog serial bus
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SClk : out std_logic; --Serial Bit clock for analog serial bus
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MClk : out std_logic--; --Master clock for analog serial bus (runs DeltaSig hardware in converters)
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);
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end component;
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component AnalogBusPorts
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port (
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SClk : in std_logic; --this whole schebang runs of the analog serial bus clock
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LRClk : in std_logic; --which channel at the moment?
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AdcData : in std_logic; --data coming in from adc
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DacData : out std_logic; --data coming in from adc
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SampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
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nSampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
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LastAdcSample : out std_logic_vector(23 downto 0); --buffer for fifo data
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NextDacSample : in std_logic_vector(23 downto 0)--; --buffer for fifo data
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);
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end component;
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signal LRClk_i : std_logic;
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signal SClk_i : std_logic;
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signal DacData_e : std_logic;
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signal DacData_i : std_logic;
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--signal count : std_logic_vector(24 downto 0);
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begin
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Clocks: ClocksPorts
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port map (
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Xtal=>Xtal,
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LRClk=>LRClk_i,
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SClk=>SClk_i,
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MClk=>MClk--,
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);
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AnalogBus: AnalogBusPorts
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port map (
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SClk=>SClk_i,
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LRClk=>LRClk_i,
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AdcData=>AdcData,
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DacData=>DacData_e,
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SampleStrobe=>LDataStrobe,
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nSampleStrobe=>RDataStrobe,
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LastAdcSample=>ADCSampleBus,
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NextDacSample=>DACSampleBus--,
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);
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LRClk <= LRClk_i;
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SClk <= SClk_i;
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DacData <= DacData_i;
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process (Xtal)
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begin
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if (Xtal'event and Xtal = '1') then
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if (nDebugLoopBack = '0') then
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DacData_i <= AdcData;
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else
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DacData_i <= DacData_e;
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end if;
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end if; --if (Xtal'event ...
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end process;
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end I2SParalell;
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