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[/] [i650/] [trunk/] [rtl/] [accumulator.v] - Diff between revs 20 and 21

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`include "defines.v"
`include "defines.v"
 
 
module accumulator (
module accumulator (
   input rst,
   input rst,
   input ap, bp, dp,
   input ap, bp, dp,
   input dx, d1, d2,
   input dx, d1, d2, d10,
   input dxu, d0u,
   input dxu, d0u,
   input wu, wl,
   input wu, wl,
   input [0:6] adder_out,
   input [0:6] adder_out, console_out,
   input acc_regen_gate, right_shift_gate, acc_ri_gate,
   input acc_regen_gate, right_shift_gate, acc_ri_gate, acc_ri_console,
         zero_shift_count, man_acc_reset, reset_op_latch,
         zero_shift_count, man_acc_reset, reset_op,
   input [0:3] early_idx, ontime_idx,
   input [0:3] early_idx, ontime_idx,
   output reg [0:6] early_out, ontime_out, ped_out
   output reg [0:6] early_out, ontime_out, ped_out
   );
   );
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // The accumulator occupies 22 locations of a 32x7bit RAM. 
   // The accumulator occupies 22 locations of a 32x7bit RAM. 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   reg [0:6] digits [0:31];
   reg [0:6] digits [0:31];
 
 
   wire [0:4] acc_early_idx  = {(dx? ~wu : wu), early_idx};
   wire [0:4] acc_early_idx  = {(d10? ~wu : wu), early_idx};
   wire [0:4] acc_ontime_idx = {wu, ontime_idx};
   wire [0:4] acc_ontime_idx = {wu, ontime_idx};
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // A -- Read into early_out from RAM
   // A -- Read into early_out from RAM
   //      Read into ontime_out
   //      Read into ontime_out
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   wire acc_reset =  reset_op_latch | man_acc_reset
   wire acc_reset =  reset_op | man_acc_reset
                   | (zero_shift_count & wl & (d1 | d2));
                   | (zero_shift_count & wl & (d1 | d2));
   always @(posedge ap)
   always @(posedge ap)
      if (rst) begin
      if (rst) begin
         early_out  <= `biq_blank;
         early_out  <= `biq_blank;
         ontime_out <= `biq_blank;
         ontime_out <= `biq_blank;
      end else begin
      end else begin
         early_out  <= reset_op_latch? `biq_0
         early_out  <= reset_op?           `biq_0
 
                     : ((wl & d10) | dxu)? early_out
                     : digits[acc_early_idx];
                     : digits[acc_early_idx];
         ontime_out <= (acc_reset | d0u | dxu)? `biq_0 : early_out;
         ontime_out <= (acc_reset | d0u | dxu)? `biq_0 : early_out;
      end;
      end;
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
Line 71... Line 72...
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   always @(posedge bp)
   always @(posedge bp)
      if (rst) begin
      if (rst) begin
         ped_out <= `biq_blank;
         ped_out <= `biq_blank;
      end else begin
      end else begin
         ped_out <= right_shift_gate? early_out
         ped_out <= acc_ri_console?   console_out
 
                  : right_shift_gate? early_out
                  : acc_ri_gate?      adder_out
                  : acc_ri_gate?      adder_out
                  : acc_regen_gate?   ontime_out
                  : acc_regen_gate?   ontime_out
                  : `biq_blank;
                  : `biq_blank;
      end;
      end;
 
 

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