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//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
`include "defines.v"
 
 
module adder (
module adder (
   input rst,
   input rst,
   input bp, dp, c_a, edxu, dx, ed0u, d1, ed1l, d10, d10u, wl,
   input ap, bp, dp,
 
         dxu, dx, d0u, d1, d1l, d10, d10u, wl,
   input [0:6] entry_a, entry_b,
   input [0:6] entry_a, entry_b,
   input tlu_on, left_shift_off, left_shift_on,
   input tlu_on, left_shift_off, left_shift_on,
   input no_carry_insert, no_carry_blank, carry_insert, carry_blank,
   input no_carry_insert, no_carry_blank, carry_insert, carry_blank,
   input zero_insert,
   input zero_insert,
 
 
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   input quotient_digit_on, overflow_stop_sw, overflow_sense_sw,
   input quotient_digit_on, overflow_stop_sw, overflow_sense_sw,
   input mult_div_off, dist_true_add_gate, acc_true_add_latch,
   input mult_div_off, dist_true_add_gate, acc_true_add_latch,
   input shift_overflow,
   input shift_overflow,
 
 
   output reg[0:6] adder_out,
   output reg[0:6] adder_out,
   output reg carry_test, no_carry_test,
   output reg carry_test, no_carry_test, d0l_carry_sig, overflow_stop,
   output d0l_carry_sig,
 
 
 
   output overflow_stop, overflow_light, overflow_sense_sig
   output overflow_light, overflow_sense_sig
   );
   );
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // The 650 adder operates like this:
   // The 650 bi-quinary adder accepts its inputs early (i.e., one clock ahead),
   //    The adder output latches are normally reset by AP except when
   // producing a result during the next digit time. This implementation retains
   //    suppressed by reset_cntrl. reset_cntrl is turned
   // sum and carries in _hold flip-flops, the 650 used other tricky means.
   //    off by (plate pullover):
 
   //       tlu_on | (cp & d1 & lt_sh_on) | (cp & ed0u & lt_sh_off)
 
   //    and on by:
 
   //       (bp & wl & d10 & lt_sh_off) | (bp & edxu & lt_sh_on)
 
   //    The carry and no_carry signals are gated by DP, which
 
   //    in turn gates the adder output. The falling edge of DP triggers
 
   //    the output latches, the pulse lasting past the reset action of
 
   //    AP.
 
   //
 
   // Schedule for this implementation:
 
   //    A : --
 
   //    B : Combinational logic begins forming new sum and carry
 
   //        Previous sum and carry brought to adder output
 
   //        Setup reset_cntrl
 
   //        Setup overflow_stop_latch
 
   //    C : --
 
   //    D : Save combinational logic new sum and carry
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
 
 
   reg [0:6] sum_hold;
   reg [0:6] sum_hold;
   reg carry_hold, no_carry_hold, carry_test_hold, no_carry_test_hold;
   reg carry_hold, no_carry_hold, carry_test_hold, no_carry_test_hold;
   reg reset_cntrl;
   reg reset_ctl;
   reg carry, no_carry;
   reg carry, no_carry;
   reg overflow_stop_latch;
 
   assign d0l_carry_sig = c_a & wl & dx & carry;
 
   assign overflow_stop = overflow_stop_latch;
 
   assign overflow_light = overflow_stop_latch;
 
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // Bi-quinary adder, forms biq sum of two biq digits with carry in and out.
   // Bi-quinary adder, forms biq sum of two biq digits with carry in and out.
   // Hand captured from 650 patent fig. 68. 
   // Hand captured from 650 patent fig. 68. 
 
   //
 
   // By design, this logic produces a sum of all zeroes with zero carry_out and 
 
   // no_carry_out whenever entry_a or entry_b or both carry and no_carry are
 
   // zero.
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   wire b0_and_b5 =  (entry_a[`biq_b0] & entry_b[`biq_b5])
   wire b0_and_b5 =  (entry_a[`biq_b0] & entry_b[`biq_b5])
                   | (entry_a[`biq_b5] & entry_b[`biq_b0]);
                   | (entry_a[`biq_b5] & entry_b[`biq_b0]);
   wire q4_a_or_b = entry_a[`biq_q4] | entry_b[`biq_q4];
   wire q4_a_or_b = entry_a[`biq_q4] | entry_b[`biq_q4];
   wire q3_a_or_b = entry_a[`biq_q3] | entry_b[`biq_q3];
   wire q3_a_or_b = entry_a[`biq_q3] | entry_b[`biq_q3];
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   wire sum_b5 = b5_no_carry | b5_carry;
   wire sum_b5 = b5_no_carry | b5_carry;
   wire [0:6] sum_out = {sum_b5, sum_b0, sum_q4, sum_q3, sum_q2, sum_q1, sum_q0};
   wire [0:6] sum_out = {sum_b5, sum_b0, sum_q4, sum_q3, sum_q2, sum_q1, sum_q0};
   wire carry_out = b0_carry | b5_carry;
   wire carry_out = b0_carry | b5_carry;
   wire no_carry_out = b0_no_carry | b5_no_carry;
   wire no_carry_out = b0_no_carry | b5_no_carry;
 
 
   wire overflow =  shift_overflow
 
                  | (carry_test & d10u & dist_true_add_gate
 
                                & acc_true_add_latch & mult_div_off);
 
   assign overflow_sense_sig = overflow & overflow_sense_sw;
 
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // B -- 
   // A : Supply sum and carries from previous digit time
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   always @(posedge rst, posedge bp) begin
   always @(posedge ap)
      if (rst) begin
      if (rst) begin
         adder_out <= `biq_blank;
         adder_out <= `biq_blank;
         reset_cntrl <= 0;
 
         carry_test <= 0;
         carry_test <= 0;
         no_carry_test <= 0;
         no_carry_test <= 0;
         carry <= 0;
         carry <= 0;
         no_carry <= 0;
         no_carry <= 0;
         overflow_stop_latch <= 0;
 
      end else begin
      end else begin
         adder_out <= sum_hold;
         adder_out <= sum_hold;
         carry_test <= carry_test_hold;
         carry_test <= carry_test_hold;
         no_carry_test <= no_carry_test_hold;
         no_carry_test <= no_carry_test_hold;
         carry <= carry_hold;
         carry <= carry_hold;
         no_carry <= no_carry_hold;
         no_carry <= no_carry_hold;
         if (tlu_on | (d1 & left_shift_on) | (ed0u & left_shift_off)) begin
 
            reset_cntrl <= 0;
 
         end else if ((wl & d10 & left_shift_off) | (edxu & left_shift_on)) begin
 
            reset_cntrl <= 1;
 
         end
 
         if (error_reset) begin
 
            overflow_stop_latch <= 0;
 
         end else if ((ed1l & carry_test & quotient_digit_on)
 
                    | (overflow & overflow_stop_sw)) begin
 
            overflow_stop_latch <= 1;
 
         end
 
      end
      end
 
 
 
   wire reset_ctl_on_p  = (wl & d10 & left_shift_off) | (dxu & left_shift_on);
 
   wire reset_ctl_off_p = tlu_on | (d1 & left_shift_on) | (d0u & left_shift_off);
 
   always @(posedge ap)
 
      if (rst) begin
 
         reset_ctl <= 0;
 
      end else if (reset_ctl_on_p) begin
 
         reset_ctl <= 1;
 
      end else if (reset_ctl_off_p) begin
 
         reset_ctl <= 0;
 
      end;
 
 
 
   wire overflow =  shift_overflow
 
                  | (carry_test & d10u & dist_true_add_gate
 
                                & acc_true_add_latch & mult_div_off);
 
   assign overflow_sense_sig = overflow & overflow_sense_sw;
 
   wire overflow_stop_p =  (d1l & carry_test & quotient_digit_on)
 
                         | (overflow & overflow_stop_sw);
 
   assign overflow_light = overflow_stop;
 
   always @(posedge bp)
 
      if (rst) begin
 
         overflow_stop <= 1;
 
      end else if (error_reset) begin
 
         overflow_stop <= 0;
 
      end else if (overflow_stop_p) begin
 
         overflow_stop <= 1;
   end;
   end;
 
 
   always @(posedge rst, posedge dp) begin
   always @(posedge dp)
 
      if (rst)                      d0l_carry_sig <= 0;
 
      else if (wl & d1)             d0l_carry_sig <= 0;
 
      else if (wl & dx & carry_out) d0l_carry_sig <= 1;
 
 
 
   always @(posedge dp)
      if (rst) begin
      if (rst) begin
         sum_hold <= `biq_blank;
         sum_hold <= `biq_blank;
         carry_hold <= 0;
         carry_hold <= 0;
         no_carry_hold <= 0;
         no_carry_hold <= 0;
         carry_test_hold <= 0;
         carry_test_hold <= 0;
         no_carry_test_hold <= 0;
         no_carry_test_hold <= 0;
      end else begin
      end else begin
         sum_hold <=      zero_insert? `biq_0
         sum_hold <=      zero_insert? `biq_0
                        : reset_cntrl?  sum_hold
                        : reset_ctl?  sum_hold
                        : sum_out;
                        : sum_out;
         carry_hold <=   (reset_cntrl | carry_blank)? 1'b0
         carry_hold    <= (reset_ctl | carry_blank)? 1'b0
                        : carry_insert? 1'b1
                        : carry_insert? 1'b1
                        : carry_out;
                        : carry_out;
         no_carry_hold <= (reset_cntrl | no_carry_blank)? 1'b0
         no_carry_hold <= (reset_ctl | no_carry_blank)? 1'b0
                        : no_carry_insert? 1'b1
                        : no_carry_insert? 1'b1
                        : no_carry_out;
                        : no_carry_out;
         carry_test_hold    <= reset_cntrl? 1'b0 : carry_out;
         carry_test_hold    <= reset_ctl? 1'b0 : carry_out;
         no_carry_test_hold <= reset_cntrl? 1'b0 : no_carry_out;
         no_carry_test_hold <= reset_ctl? 1'b0 : no_carry_out;
      end
 
   end;
   end;
 
 
 
 
endmodule
endmodule
 
 
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