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[/] [i650/] [trunk/] [rtl/] [addr_reg.v] - Diff between revs 22 and 27

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Rev 22 Rev 27
Line 41... Line 41...
    input set_8000, reset_8000,
    input set_8000, reset_8000,
    input tlu_band_change,
    input tlu_band_change,
    input double_write,
    input double_write,
    input no_write,
    input no_write,
    input bs_to_gs,
    input bs_to_gs,
    input ri_gs,
    input rigs,
    input [0:6] ps_reg_in, console_in,
    input [0:6] ps_reg_in, console_in,
    input ri_addr_reg,
    input ri_addr_reg,
    input console_to_addr_reg,
    input console_to_addr_reg,
 
 
    output reg[0:6] addr_th, addr_h, addr_t, addr_u,
    output reg[0:6] addr_th, addr_h, addr_t, addr_u,
Line 119... Line 119...
   assign addr_8xx1_p = addr_8xxx_p & addr_u[`biq_q1];
   assign addr_8xx1_p = addr_8xxx_p & addr_u[`biq_q1];
   assign addr_8xx2_p = addr_8xxx_p & addr_u[`biq_q2];
   assign addr_8xx2_p = addr_8xxx_p & addr_u[`biq_q2];
   assign addr_8xx3_p = addr_8xxx_p & addr_u[`biq_q3];
   assign addr_8xx3_p = addr_8xxx_p & addr_u[`biq_q3];
 
 
   // Memory access error
   // Memory access error
   assign mem_error_p = double_write | ((bs_to_gs | ri_gs) & ~dx & no_write);
   assign mem_error_p = double_write | ((bs_to_gs | rigs) & ~dx & no_write);
 
 
   always @(posedge ap)
   always @(posedge ap)
      if (rst) begin
      if (rst) begin
         invalid_addr <= 0;
         invalid_addr <= 0;
      end else if (error_reset | ri_addr_reg | console_to_addr_reg) begin
      end else if (error_reset | ri_addr_reg | console_to_addr_reg) begin

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