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Line 46... |
);
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);
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reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
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reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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// Calculate the early (next digit) and on-time RAM addresses. Console read
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// and write are implementation extensions.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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wire [0:14] band_addr, gs_addr, gs_addr_early;
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wire [0:14] band_addr, gs_addr, gs_addr_early;
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ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
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ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
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wire console_acc = console_read_gs | console_write_gs;
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wire console_acc = console_read_gs | console_write_gs;
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assign gs_addr = console_acc? console_ram_addr : (band_addr + dynamic_addr);
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assign gs_addr = console_acc? console_ram_addr : (band_addr + dynamic_addr);
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assign gs_addr_early = console_acc? console_ram_addr
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// The % operator fixes a spurious warning from XST synthesis due to use of a
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: (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
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// 32-bit mux for ? operator. Uses no gates.
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assign gs_addr_early = (console_acc? console_ram_addr
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: (band_addr + ((dynamic_addr + 1) % 600))) % 32768;
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//-----------------------------------------------------------------------------
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// These 650 write errors are not possible for this implementation.
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//-----------------------------------------------------------------------------
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assign double_write = 0;
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assign double_write = 0;
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assign no_write = 0;
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assign no_write = 0;
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//-----------------------------------------------------------------------------
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// A : Read from RAM at on-time address.
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//-----------------------------------------------------------------------------
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always @(posedge ap) begin
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always @(posedge ap) begin
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if (rst) begin
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if (rst) begin
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gs_out <= `biq_blank;
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gs_out <= `biq_blank;
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end else begin
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end else begin
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gs_out <= gs_mem[gs_addr];
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gs_out <= gs_mem[gs_addr];
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end
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end
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end;
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end;
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//-----------------------------------------------------------------------------
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// D : Write to RAM at early address.
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//-----------------------------------------------------------------------------
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always @(posedge dp) begin
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always @(posedge dp) begin
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if (write_gate)
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if (write_gate)
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gs_mem[gs_addr_early] <= gs_in;
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gs_mem[gs_addr_early] <= gs_in;
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end;
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end;
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