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[/] [i650/] [trunk/] [rtl/] [operator_ctl.v] - Diff between revs 12 and 13

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Rev 12 Rev 13
Line 119... Line 119...
   `define state_read_gs_2             6'd31
   `define state_read_gs_2             6'd31
   `define state_read_gs_3             6'd32
   `define state_read_gs_3             6'd32
   `define state_read_gs_4             6'd33
   `define state_read_gs_4             6'd33
   `define state_read_gs_5             6'd34
   `define state_read_gs_5             6'd34
   `define state_read_gs_6             6'd35
   `define state_read_gs_6             6'd35
 
   `define state_write_gs_1            6'd36
   `define state_clear_drum_1          6'd50
   `define state_write_gs_2            6'd37
   `define state_clear_drum_2          6'd51
   `define state_write_gs_3            6'd38
   `define state_clear_drum_3          6'd52
   `define state_write_gs_4            6'd39
 
   `define state_write_gs_5            6'd40
 
   `define state_clear_drum_1          6'd41
 
   `define state_clear_drum_2          6'd42
 
   `define state_clear_drum_3          6'd43
 
   `define state_load_gs_1             6'd44
 
   `define state_load_gs_1             6'd45
 
 
   always @(posedge clk) begin
   always @(posedge clk) begin
      if (rst) begin
      if (rst) begin
         console_to_addr  <= 0;
         console_to_addr  <= 0;
         pgm_start        <= 0;
         pgm_start        <= 0;
Line 197... Line 203...
                     end else if (do_reset_console) begin
                     end else if (do_reset_console) begin
                        do_reset_console   <= 0;
                        do_reset_console   <= 0;
                        state <= `state_reset_console_1;
                        state <= `state_reset_console_1;
                     end else if (do_clear_drum) begin
                     end else if (do_clear_drum) begin
                        do_clear_drum <= 0;
                        do_clear_drum <= 0;
                        gs_ram_addr <= 15'd0;
 
                        state <= `state_clear_drum_1;
                        state <= `state_clear_drum_1;
                     end else if (do_pgm_reset) begin
                     end else if (do_pgm_reset) begin
                        do_pgm_reset       <= 0;
                        do_pgm_reset       <= 0;
                        state <= `state_pgm_reset_1;
                        state <= `state_pgm_reset_1;
                     end else if (do_acc_reset) begin
                     end else if (do_acc_reset) begin
Line 427... Line 432...
                        busy <= 1;
                        busy <= 1;
                        state <= `state_read_gs_1;
                        state <= `state_read_gs_1;
                     end
                     end
                  end
                  end
 
 
 
                  // Write word to general storage:
 
                  //    --> 4 digits address, little-endian
 
                  //    <-- dx digit, sign digit, d1-d10
 
                  // 0: Ignore if not in manual
 
                  // 1: Readin low-order addr digit
 
                  // 2: Readin remaining addr digits
 
                  // 3: Synchronize with d10
 
                  //    digit_ready <- 1
 
                  // 4: Readin first digit
 
                  // 5: Write digit
 
                  //    Readin next digit
 
                  // 6: Cleanup
                  `cmd_write_gs: begin
                  `cmd_write_gs: begin
 
                     if (ctl_sw_manual) begin
 
                        busy <= 1;
 
                        state <= `state_write_gs_1;
 
                     end
 
                  end
                  end
                  end
 
 
                  `cmd_read_acc: begin
                  `cmd_read_acc: begin
 
 
                  end
                  end
 
 
                  `cmd_read_dist: begin
                  `cmd_read_dist: begin
                  end
                  end
 
 
Line 457... Line 479...
                        do_clear_drum <= 1;
                        do_clear_drum <= 1;
                     end
                     end
                  end
                  end
 
 
                  `cmd_load_gs: begin
                  `cmd_load_gs: begin
 
                     if (ctl_sw_manual) begin
 
                        busy <= 1;
 
                        state <= `state_load_gs_1;
 
                        digit_ready <= 1;
 
                     end
                  end
                  end
 
 
                  `cmd_dump_gs: begin
                  `cmd_dump_gs: begin
                  end
                  end
 
 
                  `cmd_power_on_reset: begin
                  `cmd_power_on_reset: begin
 
                     busy <= 1;
 
                     do_power_on_reset <= 1;
                  end
                  end
 
 
                  `cmd_reset_console: begin
                  `cmd_reset_console: begin
 
                     busy <= 1;
 
                     do_reset_console <= 1;
                  end
                  end
 
 
                  `cmd_hard_reset: begin
                  `cmd_hard_reset: begin
                     busy <= 1;
                     busy <= 1;
                     do_hard_reset <= 1;
                     do_hard_reset <= 1;
Line 688... Line 719...
            `state_read_gs_6: begin
            `state_read_gs_6: begin
               digit_ready <= 0;
               digit_ready <= 0;
               state <= `state_idle;
               state <= `state_idle;
            end
            end
 
 
 
            // Write word to general storage:
 
            //    --> 4 digits address, little-endian
 
            //    <-- dx digit, sign digit, d1-d10
 
            // 0: Ignore if not in manual
 
            // 1: Readin low-order addr digit
 
            // 2: Readin remaining addr digits
 
            // 3: Synchronize with d10
 
            //    digit_ready <- 1
 
            // 4: Readin and write digit
 
            // 5: Write digit
 
            //    Readin next digit
 
            // 6: Cleanup
 
 
 
            `state_write_gs_1: begin
 
               if (dx) begin
 
                  state <= `state_write_gs_2;
 
                  digit_ready <= 1;
 
                  gs_addr_u <= cmd_digit_in;
 
               end
 
            end
 
 
 
            `state_write_gs_2: begin
 
               if (d0) gs_addr_t <= cmd_digit_in;
 
               else if (d1) gs_addr_h <= cmd_digit_in;
 
               else if (d2) begin
 
                  gs_addr_th <= cmd_digit_in;
 
                  state <= `state_write_gs_3;
 
                  digit_ready <= 0;
 
               end
 
            end
 
 
 
            `state_write_gs_3: begin
 
               if (d10) begin
 
                  gs_ram_addr <= gs_word_addr;
 
                  digit_ready <= 1;
 
                  state <= `state_write_gs_4;
 
               end
 
            end
 
 
 
            `state_write_gs_4: begin
 
               write_gs <= 1;
 
               console_out <= cmd_digit_in;
 
               gs_ram_addr <= gs_ram_addr + 1;
 
               if (d10) begin
 
                  digit_ready <= 0;
 
                  state <= `state_write_gs_5;
 
               end
 
            end
 
 
 
            `state_write_gs_5: begin
 
               write_gs <= 0;
 
               state <= `state_idle;
 
            end
 
 
            // 0 : Ignore if not in manual
            // 0 : Ignore if not in manual
            //     Clear gs_ram_addr
            //     Clear gs_ram_addr
            // 1 : Synchronize with d10
            // 1 : Synchronize with d10
            //     Turn on console_write_gs
            //     Turn on console_write_gs
            // 2 : Put a digit:
            // 2 : Put a digit:
Line 699... Line 784...
            //     d0: minus
            //     d0: minus
            //     d1-d10: zero
            //     d1-d10: zero
            //     gs_ram_addr++
            //     gs_ram_addr++
            `state_clear_drum_1: begin
            `state_clear_drum_1: begin
               if (d10) begin
               if (d10) begin
 
                  console_out <= `biq_blank;
 
                  gs_ram_addr <= 15'd0;
 
                  write_gs <= 1;
                  state <= `state_clear_drum_2;
                  state <= `state_clear_drum_2;
               end
               end
            end
            end
 
 
            `state_clear_drum_2: begin
            `state_clear_drum_2: begin
               write_gs <= 1;
 
               console_out <= dx? `biq_blank
               console_out <= dx? `biq_blank
                            : d0? `biq_minus
                            : d0? `biq_minus
                            : `biq_0;
                            : `biq_0;
               if (write_gs)
 
                  gs_ram_addr <= gs_ram_addr + 1;
                  gs_ram_addr <= gs_ram_addr + 1;
               if (gs_ram_addr == 15'd23999) begin
               if (gs_ram_addr == 15'd23999) begin
                  write_gs <= 0;
                  write_gs <= 0;
                  state <= `state_idle;
                  state <= `state_idle;
               end
               end
            end
            end
 
 
 
            `state_load_gs_1: begin
 
               gs_ram_addr <= 15'd0;
 
               write_gs <= 1;
 
               console_out <= cmd_digit_in;
 
               state <= `state_load_gs_2;
 
            end
 
 
 
            `state_load_gs_2: begin
 
               gs_ram_addr <= gs_ram_addr + 1;
 
               console_out <= cmd_digit_in;
 
               if (gs_ram_addr == 15d'23999) begin
 
                  write_gs <= 0;
 
                  digit_ready <= 0;
 
                  state <= `state_idle;
 
               end
 
            end
 
 
         endcase;
         endcase;
      end
      end
   end;
   end;
 
 
   always @(posedge ap) begin
   always @(posedge ap) begin

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