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Line 31... |
`include "defines.v"
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`include "defines.v"
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module operator_ctl (
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module operator_ctl (
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input rst, clk,
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input rst, clk,
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input ap, dp,
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input ap, dp,
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input dx, d0, d1, d2, d3, d4, d5, d6, d10,
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input dx, d0, d1, d2, d3, d4, d5, d6, d9, d10,
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input wu, hp,
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input wu, wl, hp,
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input [0:3] early_idx, ontime_idx,
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input [0:3] early_idx, ontime_idx,
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input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
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input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
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prog_ontime,
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prog_ontime,
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input [0:5] command,
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input [0:5] command,
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Line 47... |
output reg[0:14] gs_ram_addr,
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output reg[0:14] gs_ram_addr,
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output reg read_gs, write_gs,
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output reg read_gs, write_gs,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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storage_control,
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storage_control,
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output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
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output reg man_pgm_reset, man_acc_reset, hard_reset,
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hard_reset,
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output set_8000, reset_8000,
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output reg[0:6] cmd_digit_out,
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output reg[0:6] cmd_digit_out,
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output reg busy, digit_ready,
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output reg busy, digit_ready,
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output reg punch_card, read_card, card_digit_ready
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output reg punch_card, read_card, card_digit_ready
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);
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);
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Line 75... |
assign storage_control = run_control | disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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assign display_digit = (disp_sw_lacc | disp_sw_uacc)? acc_ontime
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assign display_digit = (disp_sw_lacc | disp_sw_uacc)? acc_ontime
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: (disp_sw_dist | disp_sw_ri | disp_sw_ro)? dist_ontime
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: (disp_sw_dist | disp_sw_ri | disp_sw_ro)? dist_ontime
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: disp_sw_pgm? prog_ontime
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: disp_sw_pgm? prog_ontime
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: `biq_blank;
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: `biq_blank;
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assign set_8000 = man_pgm_reset & (ctl_sw_addr_stop | ctl_sw_run);
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assign reset_8000 = man_pgm_reset & ctl_sw_manual;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Calculate the RAM address of the general storage word at address gs_addr_.
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// Calculate the RAM address of the general storage word at address gs_addr_.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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`define state_read_gs_4 6'd33
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`define state_read_gs_4 6'd33
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`define state_read_gs_5 6'd34
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`define state_read_gs_5 6'd34
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`define state_read_gs_6 6'd35
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`define state_read_gs_6 6'd35
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`define state_write_gs_1 6'd36
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`define state_write_gs_1 6'd36
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`define state_write_gs_2 6'd37
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`define state_write_gs_2 6'd37
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`define state_write_gs_2a 6'd63
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`define state_write_gs_3 6'd38
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`define state_write_gs_3 6'd38
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`define state_write_gs_4 6'd39
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`define state_write_gs_4 6'd39
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`define state_write_gs_5 6'd40
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`define state_write_gs_5 6'd40
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`define state_clear_drum_1 6'd41
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`define state_read_acc_1 6'd41
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`define state_clear_drum_2 6'd42
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`define state_read_acc_2 6'd42
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`define state_clear_drum_3 6'd43
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`define state_read_acc_3 6'd43
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`define state_load_gs_1 6'd44
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`define state_read_dist_1 6'd44
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`define state_load_gs_2 6'd45
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`define state_read_dist_2 6'd45
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`define state_dump_gs_1 6'd46
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`define state_read_dist_3 6'd46
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`define state_dump_gs_2 6'd47
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`define state_read_prog_1 6'd47
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`define state_dump_gs_3 6'd48
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`define state_read_prog_2 6'd48
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`define state_dump_gs_4 6'd49
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`define state_read_prog_3 6'd49
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`define state_clear_drum_1 6'd50
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`define state_clear_drum_2 6'd51
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`define state_clear_drum_3 6'd52
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`define state_load_gs_1 6'd53
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`define state_load_gs_2 6'd54
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`define state_dump_gs_1 6'd55
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`define state_dump_gs_2 6'd56
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`define state_dump_gs_3 6'd57
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`define state_dump_gs_4 6'd58
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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pgm_stop <= 0;
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pgm_stop <= 0;
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err_reset <= 0;
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err_reset <= 0;
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err_sense_reset <= 0;
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err_sense_reset <= 0;
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man_pgm_reset <= 0;
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man_pgm_reset <= 0;
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man_acc_reset <= 0;
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man_acc_reset <= 0;
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set_8000 <= 0;
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reset_8000 <= 0;
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hard_reset <= 0;
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hard_reset <= 0;
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// reset console switches
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// reset console switches
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pgm_sw_stop <= 0;
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pgm_sw_stop <= 0;
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pgm_sw_run <= 1;
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pgm_sw_run <= 1;
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Line 472... |
state <= `state_write_gs_1;
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state <= `state_write_gs_1;
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end
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end
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end
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end
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`cmd_read_acc: begin
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`cmd_read_acc: begin
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busy <= 1;
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state <= `state_read_acc_1;
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end
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end
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`cmd_read_dist: begin
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`cmd_read_dist: begin
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busy <= 1;
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state <= `state_read_dist_1;
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end
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end
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`cmd_read_prog: begin
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`cmd_read_prog: begin
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busy <= 1;
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state <= `state_read_prog_1;
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end
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end
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// 0 : Ignore if not in manual
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// 0 : Ignore if not in manual
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// Clear gs_ram_addr
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// Clear gs_ram_addr
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// 1 : Synchronize with d10
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// 1 : Synchronize with d10
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Line 778... |
state <= `state_write_gs_3;
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state <= `state_write_gs_3;
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digit_ready <= 0;
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digit_ready <= 0;
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end
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end
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end
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end
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`state_write_gs_2a: begin
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if (d9) begin
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digit_ready <= 1;
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state <= `state_write_gs_3;
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end
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end
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`state_write_gs_3: begin
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`state_write_gs_3: begin
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if (d10) begin
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if (d10) begin
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gs_ram_addr <= gs_word_addr;
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gs_ram_addr <= gs_word_addr;
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digit_ready <= 1;
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digit_ready <= 1;
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state <= `state_write_gs_4;
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state <= `state_write_gs_4;
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Line 796... |
end
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end
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`state_write_gs_4: begin
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`state_write_gs_4: begin
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write_gs <= 1;
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write_gs <= 1;
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console_out <= cmd_digit_in;
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console_out <= cmd_digit_in;
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if (write_gs)
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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if (d10) begin
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if (d10) begin
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digit_ready <= 0;
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digit_ready <= 0;
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state <= `state_write_gs_5;
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state <= `state_write_gs_5;
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end
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end
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Line 809... |
`state_write_gs_5: begin
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`state_write_gs_5: begin
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write_gs <= 0;
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write_gs <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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`state_read_acc_1: begin
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if (wl & d10) begin
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state <= `state_read_acc_2;
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end
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end
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`state_read_acc_2: begin
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digit_ready <= 1;
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cmd_digit_out <= acc_ontime;
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if (wu & d10) begin
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state <= `state_read_acc_3;
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end
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end
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`state_read_acc_3: begin
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digit_ready <= 0;
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state <= `state_idle;
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end
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`state_read_dist_1: begin
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if (d10) begin
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state <= `state_read_dist_2;
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end
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end
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`state_read_dist_2: begin
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digit_ready <= 1;
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cmd_digit_out <= dist_ontime;
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if (d10) begin
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state <= `state_read_dist_3;
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end
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end
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`state_read_dist_3: begin
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digit_ready <= 0;
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state <= `state_idle;
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end
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`state_read_prog_1: begin
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if (d10) begin
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state <= `state_read_prog_2;
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end
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end
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`state_read_prog_2: begin
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digit_ready <= 1;
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cmd_digit_out <= prog_ontime;
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if (d10) begin
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state <= `state_read_prog_3;
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end
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end
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`state_read_prog_3: begin
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digit_ready <= 0;
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state <= `state_idle;
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end
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// 0 : Ignore if not in manual
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// 0 : Ignore if not in manual
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// 1 : Synchronize with dx
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// 1 : Synchronize with dx
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// Put first dx digit
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// Put first dx digit
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// 2 : Put a digit:
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// 2 : Put a digit:
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// dx: blank
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// dx: blank
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