| Line 129... |
Line 129... |
`define state_read_gs_4 6'd33
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`define state_read_gs_4 6'd33
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`define state_read_gs_5 6'd34
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`define state_read_gs_5 6'd34
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`define state_read_gs_6 6'd35
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`define state_read_gs_6 6'd35
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`define state_write_gs_1 6'd36
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`define state_write_gs_1 6'd36
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`define state_write_gs_2 6'd37
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`define state_write_gs_2 6'd37
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`define state_write_gs_2a 6'd63
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`define state_write_gs_3 6'd38
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`define state_write_gs_3 6'd38
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`define state_write_gs_4 6'd39
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`define state_write_gs_4 6'd39
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`define state_write_gs_5 6'd40
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`define state_write_gs_5 6'd40
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`define state_read_acc_1 6'd41
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`define state_read_acc_1 6'd41
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`define state_read_acc_2 6'd42
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`define state_read_acc_2 6'd42
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| Line 152... |
Line 151... |
`define state_dump_gs_1 6'd55
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`define state_dump_gs_1 6'd55
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`define state_dump_gs_2 6'd56
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`define state_dump_gs_2 6'd56
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`define state_dump_gs_3 6'd57
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`define state_dump_gs_3 6'd57
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`define state_dump_gs_4 6'd58
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`define state_dump_gs_4 6'd58
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always @(posedge clk) begin
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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pgm_stop <= 0;
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pgm_stop <= 0;
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err_reset <= 0;
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err_reset <= 0;
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| Line 778... |
Line 777... |
state <= `state_write_gs_3;
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state <= `state_write_gs_3;
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digit_ready <= 0;
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digit_ready <= 0;
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end
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end
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end
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end
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`state_write_gs_2a: begin
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if (d9) begin
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digit_ready <= 1;
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state <= `state_write_gs_3;
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end
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end
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`state_write_gs_3: begin
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`state_write_gs_3: begin
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if (d10) begin
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if (d10) begin
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gs_ram_addr <= gs_word_addr;
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gs_ram_addr <= gs_word_addr;
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digit_ready <= 1;
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digit_ready <= 1;
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state <= `state_write_gs_4;
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state <= `state_write_gs_4;
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| Line 937... |
Line 929... |
read_gs <= 0;
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read_gs <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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endcase;
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endcase;
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end
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end;
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end;
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always @(posedge ap) begin
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always @(posedge ap)
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if (hard_reset) begin
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if (hard_reset) begin
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data_out <= `biq_blank;
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data_out <= `biq_blank;
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addr_out <= `biq_blank;
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addr_out <= `biq_blank;
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end else begin
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end else begin
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data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
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data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
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addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
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addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
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end
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end;
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end;
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always @(posedge ap) begin
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always @(posedge ap)
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if (hard_reset) begin
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if (hard_reset) begin
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punch_card <= 0;
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punch_card <= 0;
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read_card <= 0;
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read_card <= 0;
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card_digit_ready <= 0;
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card_digit_ready <= 0;
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end
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end;
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end;
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endmodule
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endmodule
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