| Line 48... |
Line 48... |
output reg[0:14] gs_ram_addr,
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output reg[0:14] gs_ram_addr,
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output reg read_gs, write_gs,
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output reg read_gs, write_gs,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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storage_control, err_restart_sw, ovflw_stop_sw, ovflw_sense_sw,
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storage_control, err_restart_sw, ovflw_stop_sw, ovflw_sense_sw,
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pgm_stop_sw,
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output reg man_pgm_reset, man_acc_reset, hard_reset,
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output reg man_pgm_reset, man_acc_reset, hard_reset,
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output set_8000, reset_8000,
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output set_8000, reset_8000,
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|
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output reg[0:6] cmd_digit_out,
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output reg[0:6] cmd_digit_out,
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output reg busy, digit_ready, restart_reset_busy,
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output reg busy, digit_ready, restart_reset_busy,
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| Line 81... |
Line 82... |
assign set_8000 = man_pgm_reset & (ctl_sw_addr_stop | ctl_sw_run);
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assign set_8000 = man_pgm_reset & (ctl_sw_addr_stop | ctl_sw_run);
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assign reset_8000 = man_pgm_reset & ctl_sw_manual;
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assign reset_8000 = man_pgm_reset & ctl_sw_manual;
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assign err_restart_sw = err_sw_sense;
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assign err_restart_sw = err_sw_sense;
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assign ovflw_stop_sw = ovflw_sw_stop;
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assign ovflw_stop_sw = ovflw_sw_stop;
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assign ovflw_sense_sw = ovflw_sw_sense;
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assign ovflw_sense_sw = ovflw_sw_sense;
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assign pgm_stop_sw = pgm_sw_stop;
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|
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Calculate the RAM address of the general storage word at address gs_addr_.
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// Calculate the RAM address of the general storage word at address gs_addr_.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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| Line 158... |
Line 160... |
`define state_dump_gs_1 6'd58
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`define state_dump_gs_1 6'd58
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`define state_dump_gs_2 6'd59
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`define state_dump_gs_2 6'd59
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`define state_dump_gs_3 6'd60
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`define state_dump_gs_3 6'd60
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`define state_dump_gs_4 6'd61
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`define state_dump_gs_4 6'd61
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|
|
always @(posedge clk)
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always @(posedge dp, posedge rst)
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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pgm_stop <= 0;
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pgm_stop <= 0;
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err_reset <= 0;
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err_reset <= 0;
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| Line 208... |
Line 210... |
gs_ram_addr <= 15'd0;
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gs_ram_addr <= 15'd0;
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read_gs <= 0;
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read_gs <= 0;
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write_gs <= 0;
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write_gs <= 0;
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acc_ri_console <= 0;
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acc_ri_console <= 0;
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console_out <= `biq_blank;
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console_out <= `biq_blank;
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end else if (dp) begin
|
end else begin
|
case (state)
|
case (state)
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`state_idle: begin
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`state_idle: begin
|
case (command)
|
case (command)
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`cmd_none: begin
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`cmd_none: begin
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if (restart_reset) begin
|
if (restart_reset) begin
|
