| Line 41... |
Line 41... |
input [0:5] command,
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input [0:5] command,
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|
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output reg[0:6] data_out, addr_out,
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output reg[0:6] data_out, addr_out,
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output reg console_to_addr,
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output reg console_to_addr,
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output reg[0:14] gs_ram_addr,
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output reg[0:14] gs_ram_addr,
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output reg read_gs, write_gs,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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storage_control,
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storage_control,
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output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
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output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
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| Line 73... |
Line 74... |
reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
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reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
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do_pgm_reset, do_acc_reset;
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do_pgm_reset, do_acc_reset;
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reg [0:5] state;
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reg [0:5] state;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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wire [0:14] gs_band_addr, gs_word_offset;
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wire [0:14] gs_band_addr;
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ram_band_addr rba(gs_addr_th[`biq_q1], gs_addr_h, gs_addr_t[`biq_b5],
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wire [0:9] gs_word_offset;
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gs_band_addr);
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ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);
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ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
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ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
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wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
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wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
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|
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`define state_idle 6'd0
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`define state_idle 6'd0
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| Line 108... |
Line 109... |
|
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`define state_read_gs_1 6'd31
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`define state_read_gs_1 6'd31
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`define state_read_gs_2 6'd32
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`define state_read_gs_2 6'd32
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`define state_read_gs_3 6'd33
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`define state_read_gs_3 6'd33
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`define state_read_gs_4 6'd34
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`define state_read_gs_4 6'd34
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`define state_read_gs_5 6'd35
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|
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Operator console state machine
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// Operator console state machine
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge dp) begin
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always @(posedge rst, posedge dp) begin
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| Line 154... |
Line 156... |
do_err_sense_reset <= 0;
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do_err_sense_reset <= 0;
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do_pgm_reset <= 0;
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do_pgm_reset <= 0;
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do_acc_reset <= 0;
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do_acc_reset <= 0;
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|
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gs_ram_addr <= 15'd0;
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gs_ram_addr <= 15'd0;
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read_gs <= 0;
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write_gs <= 0;
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end else begin
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end else begin
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case (state)
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case (state)
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`state_idle: begin
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`state_idle: begin
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case (command)
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case (command)
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`cmd_none: begin
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`cmd_none: begin
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| Line 392... |
Line 395... |
if (ctl_sw_manual) begin
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if (ctl_sw_manual) begin
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busy <= 1;
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busy <= 1;
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state <= `state_read_gs_1;
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state <= `state_read_gs_1;
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end
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end
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end
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end
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`ifdef 0
|
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`cmd_write_gs:
|
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`cmd_read_acc:
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`cmd_write_gs: begin
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`cmd_read_dist:
|
end
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`cmd_read_prog:
|
|
`cmd_clear_gs:
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`cmd_read_acc: begin
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`cmd_load_gs:
|
end
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`cmd_dump_gs:
|
|
`cmd_power_on_reset:
|
`cmd_read_dist: begin
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`cmd_reset_console:
|
end
|
`endif
|
|
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`cmd_read_prog: begin
|
|
end
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|
|
|
// 0 : Ignore if not in manual
|
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// Clear gs_ram_addr
|
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// 1 : Synchronize with d10
|
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// Turn on console_write_gs
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// 2 : Put a digit:
|
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// dx: blank
|
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// d0: minus
|
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// d1-d10: zero
|
|
// gs_ram_addr++
|
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`cmd_clear_gs: begin
|
|
|
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end
|
|
|
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`cmd_load_gs: begin
|
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end
|
|
|
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`cmd_dump_gs: begin
|
|
end
|
|
|
|
`cmd_power_on_reset: begin
|
|
end
|
|
|
|
`cmd_reset_console: begin
|
|
end
|
|
|
endcase;
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endcase;
|
end
|
end
|
|
|
// Reset console
|
// Reset console
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| Line 589... |
Line 619... |
`state_read_gs_3: begin
|
`state_read_gs_3: begin
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gs_ram_addr <= gs_word_addr;
|
gs_ram_addr <= gs_word_addr;
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state <= `state_read_gs_4;
|
state <= `state_read_gs_4;
|
end
|
end
|
|
|
|
`state_read_gs_4: begin
|
|
|
|
state <= `state_read_gs_5;
|
|
end
|
|
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endcase;
|
endcase;
|
end
|
end
|
end;
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end;
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|
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always @(posedge rst, posedge ap) begin
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always @(posedge rst, posedge ap) begin
|
