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[/] [i650/] [trunk/] [rtl/] [ram_band_addr.v] - Diff between revs 7 and 9

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Rev 7 Rev 9
Line 29... Line 29...
//
//
// You should have received a copy of the GNU Lesser General
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
 
`include "defines.v"
 
 
module ram_band_addr (
module ram_band_addr (
   input       addr_th_q1,
   input [0:6] addr_th, addr_h, addr_t,
   input [0:6] addr_h,
 
   input       addr_t_b5,
 
   output reg  [0:14] origin
   output reg  [0:14] origin
   );
   );
 
 
   always @(*) begin
   always @(*) begin
      case({addr_th_q1, addr_h, addr_t_b5})
      case ({addr_th[`biq_q1], addr_h, addr_t[`biq_b5]})
         9'b0_01_00001_0: origin = 15'd0;
         9'b0_01_00001_0: origin = 15'd0;
         9'b0_01_00001_1: origin = 15'd600;
         9'b0_01_00001_1: origin = 15'd600;
         9'b0_01_00010_0: origin = 15'd1200;
         9'b0_01_00010_0: origin = 15'd1200;
         9'b0_01_00010_1: origin = 15'd1800;
         9'b0_01_00010_1: origin = 15'd1800;
         9'b0_01_00100_0: origin = 15'd2400;
         9'b0_01_00100_0: origin = 15'd2400;

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