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https://opencores.org/ocsvn/i650/i650/trunk
[/] [i650/] [trunk/] [rtl/] [ram_band_addr.v] - Diff between revs 7 and 9
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| Rev 7 |
Rev 9 |
| Line 29... |
Line 29... |
//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module ram_band_addr (
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module ram_band_addr (
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input addr_th_q1,
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input [0:6] addr_th, addr_h, addr_t,
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input [0:6] addr_h,
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input addr_t_b5,
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output reg [0:14] origin
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output reg [0:14] origin
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);
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);
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always @(*) begin
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always @(*) begin
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case({addr_th_q1, addr_h, addr_t_b5})
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case ({addr_th[`biq_q1], addr_h, addr_t[`biq_b5]})
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9'b0_01_00001_0: origin = 15'd0;
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9'b0_01_00001_0: origin = 15'd0;
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9'b0_01_00001_1: origin = 15'd600;
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9'b0_01_00001_1: origin = 15'd600;
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9'b0_01_00010_0: origin = 15'd1200;
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9'b0_01_00010_0: origin = 15'd1200;
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9'b0_01_00010_1: origin = 15'd1800;
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9'b0_01_00010_1: origin = 15'd1800;
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9'b0_01_00100_0: origin = 15'd2400;
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9'b0_01_00100_0: origin = 15'd2400;
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