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https://opencores.org/ocsvn/i650/i650/trunk
[/] [i650/] [trunk/] [rtl/] [timing.v] - Diff between revs 18 and 20
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| Rev 18 |
Rev 20 |
| Line 43... |
Line 43... |
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output reg[0:9] digit_idx,
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output reg[0:9] digit_idx,
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output reg[0:3] early_idx, ontime_idx
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output reg[0:3] early_idx, ontime_idx
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);
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);
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reg ctr_reset;
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reg[0:3] digit_ctr;
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reg[0:3] digit_ctr;
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reg[0:3] word_ctr;
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reg[0:3] word_ctr;
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reg[0:2] sector_ctr;
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reg[0:2] sector_ctr;
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assign dxl = dx & wl;
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assign dxl = dx & wl;
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| Line 59... |
Line 60... |
assign d10u = d10 & wu;
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assign d10u = d10 & wu;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// 650 four-phase clock
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// 650 four-phase clock
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge clk) begin
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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ctr_reset <= 1;
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ap <= 1;
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ap <= 1;
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bp <= 0;
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bp <= 0;
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cp <= 0;
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cp <= 0;
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dp <= 0;
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dp <= 0;
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end else begin
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end else begin
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if (dp) ctr_reset <= 0;
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ap <= dp;
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ap <= dp;
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bp <= ap;
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bp <= ap;
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cp <= bp;
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cp <= bp;
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dp <= cp;
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dp <= cp;
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end;
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end;
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end;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Counter-based timing signals
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// Counter-based timing signals
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge dp) begin
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always @(posedge dp)
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if (rst) begin
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if (ctr_reset) begin
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dx <= 0;
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dx <= 0;
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d0 <= 0;
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d0 <= 0;
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d1 <= 0;
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d1 <= 0;
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d2 <= 0;
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d2 <= 0;
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d3 <= 0;
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d3 <= 0;
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| Line 240... |
Line 242... |
d5_d10 <= 0;
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d5_d10 <= 0;
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d10_d1_d5 <= 1;
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d10_d1_d5 <= 1;
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end
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end
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endcase;
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endcase;
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end;
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end;
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end;
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endmodule
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endmodule
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