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[/] [i650/] [trunk/] [rtl/] [timing.v] - Diff between revs 18 and 20

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Rev 18 Rev 20
Line 43... Line 43...
 
 
      output reg[0:9] digit_idx,
      output reg[0:9] digit_idx,
      output reg[0:3] early_idx, ontime_idx
      output reg[0:3] early_idx, ontime_idx
   );
   );
 
 
 
   reg ctr_reset;
   reg[0:3] digit_ctr;
   reg[0:3] digit_ctr;
   reg[0:3] word_ctr;
   reg[0:3] word_ctr;
   reg[0:2] sector_ctr;
   reg[0:2] sector_ctr;
 
 
   assign dxl = dx & wl;
   assign dxl = dx & wl;
Line 59... Line 60...
   assign d10u = d10 & wu;
   assign d10u = d10 & wu;
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // 650 four-phase clock
   // 650 four-phase clock
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   always @(posedge rst, posedge clk) begin
   always @(posedge clk)
      if (rst) begin
      if (rst) begin
 
         ctr_reset <= 1;
         ap <= 1;
         ap <= 1;
         bp <= 0;
         bp <= 0;
         cp <= 0;
         cp <= 0;
         dp <= 0;
         dp <= 0;
      end else begin
      end else begin
 
         if (dp) ctr_reset <= 0;
         ap <= dp;
         ap <= dp;
         bp <= ap;
         bp <= ap;
         cp <= bp;
         cp <= bp;
         dp <= cp;
         dp <= cp;
      end;
      end;
   end;
 
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // Counter-based timing signals
   // Counter-based timing signals
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   always @(posedge rst, posedge dp) begin
   always @(posedge dp)
      if (rst) begin
      if (ctr_reset) begin
         dx <= 0;
         dx <= 0;
         d0 <= 0;
         d0 <= 0;
         d1 <= 0;
         d1 <= 0;
         d2 <= 0;
         d2 <= 0;
         d3 <= 0;
         d3 <= 0;
Line 240... Line 242...
                     d5_d10 <= 0;
                     d5_d10 <= 0;
                     d10_d1_d5 <= 1;
                     d10_d1_d5 <= 1;
                  end
                  end
         endcase;
         endcase;
      end;
      end;
   end;
 
 
 
endmodule
endmodule
 
 
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