| Line 3... |
Line 3... |
// IBM 650 Reconstruction in Verilog (i650)
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// IBM 650 Reconstruction in Verilog (i650)
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//
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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// http:////www.opencores.org/project,i650
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//
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//
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// Description: Table lookup.
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// Description: Table look-up.
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//
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//
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// Additional Comments: See US 2959351, Fig. 86.
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// Additional Comments: See US 2959351, Fig. 86.
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//
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//
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// Copyright (c) 2015 Robert Abeles
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// Copyright (c) 2015 Robert Abeles
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//
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//
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| Line 161... |
Line 161... |
assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
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assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
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|
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always @(posedge bp)
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always @(posedge bp)
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if (rst) begin
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if (rst) begin
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prog_ped_regen_latch <= 0;
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prog_ped_regen_latch <= 0;
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end else if (~prog_add_on_p)
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end else if (~prog_add_on_p) begin
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prog_ped_regen_latch <= 0;
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prog_ped_regen_latch <= 0;
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end else if (wp) begin
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end else if (dx) begin
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prog_ped_regen_latch <= 1;
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prog_ped_regen_latch <= 1;
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end;
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end;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// TLU Carry Latch
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// TLU Carry Latch
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| Line 179... |
Line 179... |
reg tlu_carry;
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reg tlu_carry;
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|
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always @(posedge ap)
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always @(posedge ap)
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if (rst) begin
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if (rst) begin
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tlu_carry <= 0;
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tlu_carry <= 0;
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end else if (edx) begin
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end else if (dx) begin
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tlu_carry <= tlu_control & (carry_test_latch | tlu_or_acc_zero_check);
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tlu_carry <= tlu_control & (carry_test_latch | tlu_or_acc_zero_check);
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end;
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end;
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|
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wire tlu_carry_off_sig;
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wire tlu_carry_off_sig;
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digit_pulse tc_sig (rst, bp, ~tlu_carry, 1'b1, tlu_carry_off_sig);
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digit_pulse tc_sig (rst, bp, ~tlu_carry, 1'b1, tlu_carry_off_sig);
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