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[/] [i650/] [trunk/] [rtl/] [tlu.v] - Diff between revs 26 and 27

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Rev 26 Rev 27
Line 46... Line 46...
    input dist_compl_add,
    input dist_compl_add,
    input any_left_shift_on, right_shift_on, left_shift_on, mult_div_left_shift,
    input any_left_shift_on, right_shift_on, left_shift_on, mult_div_left_shift,
    input sig_digit_on, hc_add_5, mult_on, acc_true_add_gate,
    input sig_digit_on, hc_add_5, mult_on, acc_true_add_gate,
 
 
    output tlu_on, early_dist_zero_entry, early_dist_zero_control,
    output tlu_on, early_dist_zero_entry, early_dist_zero_control,
    output reg prog_ped_regen_latch, prog_to_acc_add, prog_add,
    output reg prog_to_acc_add, prog_add,
    output prog_add_d0,
    output prog_add_d0,
    output prog_ped_regen,
    output prog_ped_regen,
    output [0:9] special_digit,
    output [0:9] special_digit,
    output tlu_band_change, dist_blank_gate
    output tlu_band_change, dist_blank_gate, sel_stor_add_gate,
 
           ontime_dist_add_gate, upper_lower_check
    );
    );
 
 
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
   // Distributor zero entry and control gates
   // Distributor zero entry and control gates
   //
   //
Line 156... Line 157...
   // [124:75] TLU program regeneration control latch 1194 (Fig. 86b). Off with
   // [124:75] TLU program regeneration control latch 1194 (Fig. 86b). Off with
   // same conditions which turn TLU program add latch on. On with the next WP.
   // same conditions which turn TLU program add latch on. On with the next WP.
   // When off, interrupts program register regeneration by blocking the path
   // When off, interrupts program register regeneration by blocking the path
   // between program on time latch outputs and pedistal lines.
   // between program on time latch outputs and pedistal lines.
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
 
   reg prog_ped_regen_latch;
   assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
   assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
 
 
   always @(posedge bp)
   always @(posedge bp)
      if (rst) begin
      if (rst) begin
         prog_ped_regen_latch <= 0;
         prog_ped_regen_latch <= 0;
      end else if (~prog_add_on_p) begin
      end else if (prog_add_on_p) begin
         prog_ped_regen_latch <= 0;
         prog_ped_regen_latch <= 0;
      end else if (dx) begin
      end else if (dx) begin
         prog_ped_regen_latch <= 1;
         prog_ped_regen_latch <= 1;
      end;
      end;
 
 
Line 237... Line 239...
               | (tlu_carry_d4 & w1)
               | (tlu_carry_d4 & w1)
               | (d5_tlu_carry_no_w0 & s0)
               | (d5_tlu_carry_no_w0 & s0)
               | (d5_tlu_carry_w0 & s1)
               | (d5_tlu_carry_w0 & s1)
               | prog_to_acc_add
               | prog_to_acc_add
               | (acc_minus_sign & compl_adj)
               | (acc_minus_sign & compl_adj)
               | (quot_digit_on & edxl)
               | (quot_digit_on & dxl)
               | (edxl & dist_compl_add)
               | (dxl & dist_compl_add)
               | (~add_1 & any_left_shift_on & ~edxl);
               | (~add_1 & any_left_shift_on & ~dxl);
   wire add_1 =  (tlu_carry_d4 & w2)
   wire add_1 =  (tlu_carry_d4 & w2)
               | (d5_tlu_carry_no_w0 & s1)
               | (d5_tlu_carry_no_w0 & s1)
               | (d5_tlu_carry_w0 & s2)
               | (d5_tlu_carry_w0 & s2)
               | (edxl & (right_shift_on | left_shift_on | mult_div_left_shift))
               | (dxl & (right_shift_on | left_shift_on | mult_div_left_shift))
               | (dist_compl_add & quot_digit_on & ed0l)
               | (dist_compl_add & quot_digit_on & d0l)
               | sig_digit_on;
               | sig_digit_on;
   wire add_2 =  (tlu_carry_d4 & w3)
   wire add_2 =  (tlu_carry_d4 & w3)
               | (d5_tlu_carry_no_w0 & s2)
               | (d5_tlu_carry_no_w0 & s2)
               | (d5_tlu_carry_w0 & s3);
               | (d5_tlu_carry_w0 & s3);
   wire add_3 =  (tlu_carry_d4 & w4)
   wire add_3 =  (tlu_carry_d4 & w4)
Line 256... Line 258...
               | (d5_tlu_carry_w0 & s4);
               | (d5_tlu_carry_w0 & s4);
   wire add_4 =  (tlu_carry_d4 & w5)
   wire add_4 =  (tlu_carry_d4 & w5)
               | (d5_tlu_carry_no_w0 & s4);
               | (d5_tlu_carry_no_w0 & s4);
   wire add_5 =  (tlu_band_change & d5)
   wire add_5 =  (tlu_band_change & d5)
               | (tlu_carry_d4 & w6)
               | (tlu_carry_d4 & w6)
               | (edxl & hc_add_5);
               | (dxl & hc_add_5);
   wire add_6 =  (tlu_carry_d4 & w7);
   wire add_6 =  (tlu_carry_d4 & w7);
   wire add_7 =  (tlu_carry_d4 & w8);
   wire add_7 =  (tlu_carry_d4 & w8);
   wire add_8 =  (tlu_carry_d4 & w9);
   wire add_8 =  (tlu_carry_d4 & w9);
   wire add_9 =  (tlu_carry_d4 & w0)
   wire add_9 =  (tlu_carry_d4 & w0)
               | (d10u & mult_on & acc_true_add_gate);
               | (d10u & mult_on & acc_true_add_gate);
Line 307... Line 309...
   // a negative S4, W8, and 9 gate to provide the TLU selected storage add gate
   // a negative S4, W8, and 9 gate to provide the TLU selected storage add gate
   // from the output of cathode follower 1035 and TLU on time distributor add
   // from the output of cathode follower 1035 and TLU on time distributor add
   // gate from cathode follower 1036 for D1 through D10 of each word of the band
   // gate from cathode follower 1036 for D1 through D10 of each word of the band
   // except words 48 and 49.
   // except words 48 and 49.
   //-----------------------------------------------------------------------------
   //-----------------------------------------------------------------------------
 
   assign sel_stor_add_gate = 1'b0;
 
   assign ontime_dist_add_gate = 1'b0;
 
   assign upper_lower_check = 1'b0;
 
 
endmodule
endmodule
 
 
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