| Line 136... |
Line 136... |
wire [0:6] ar_addr_th, ar_addr_h, ar_addr_t, ar_addr_u;
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wire [0:6] ar_addr_th, ar_addr_h, ar_addr_t, ar_addr_u;
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wire ar_dynamic_addr_hit, ar_addr_no_800x, ar_addr_8000, ar_addr_8001,
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wire ar_dynamic_addr_hit, ar_addr_no_800x, ar_addr_8000, ar_addr_8001,
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ar_addr_8002, ar_addr_8003, ar_addr_8002_8003, ar_invalid_addr;
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ar_addr_8002, ar_addr_8003, ar_addr_8002_8003, ar_invalid_addr;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Arithmetic control
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//-----------------------------------------------------------------------------
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wire at_end_of_operation, at_arith_restart_d5, at_zero_insert, at_carry_blank,
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at_no_carry_blank, at_carry_insert, at_no_carry_insert, at_compl_adj,
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at_divide, at_multiply, at_acc_true_add, at_half_correct, at_hc_add_5;
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//-----------------------------------------------------------------------------
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// Accumulator and TLU validity checking
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// Accumulator and TLU validity checking
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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wire ca_acc_zero, ca_acc_no_zero, ca_check_latch;
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wire ca_acc_zero, ca_acc_no_zero, ca_check_latch;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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| Line 245... |
Line 252... |
.acc_early_out(ac_early_out),
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.acc_early_out(ac_early_out),
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.acc_ontime_out(ac_ontime_out),
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.acc_ontime_out(ac_ontime_out),
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.prog_step_early_out(ps_early_out),
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.prog_step_early_out(ps_early_out),
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.select_storage_out(ss_selected_out),
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.select_storage_out(ss_selected_out),
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.addr_u(ar_addr_u),
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.addr_u(ar_addr_u),
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.acc_true_add_gate(1'b0), // 85o
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.acc_true_add_gate(at_acc_true_add),
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.acc_compl_add_gate(1'b0), // 85r
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.acc_compl_add_gate(1'b0), // 85r
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.left_shift_gate(1'b0), // 85b
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.left_shift_gate(1'b0), // 85b
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.prog_step_add_gate(tl_prog_add),
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.prog_step_add_gate(tl_prog_add),
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.shift_num_gate(1'b0), // 85a
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.shift_num_gate(1'b0), // 85a
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.select_stor_add_gate(tl_sel_stor_add_gate),
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.select_stor_add_gate(tl_sel_stor_add_gate),
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| Line 314... |
Line 321... |
.entry_a(aa_entry_a),
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.entry_a(aa_entry_a),
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.entry_b(ab_entry_b),
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.entry_b(ab_entry_b),
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.tlu_on(tl_tlu_on),
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.tlu_on(tl_tlu_on),
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.left_shift_off(1'b1), // 85d
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.left_shift_off(1'b1), // 85d
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.left_shift_on(1'b0), // 85d
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.left_shift_on(1'b0), // 85d
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.no_carry_insert(1'b0), // 85e
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.no_carry_insert(at_no_carry_insert),
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.no_carry_blank(1'b0), // 85e
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.no_carry_blank(at_no_carry_blank),
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.carry_insert(1'b0), // 85e
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.carry_insert(at_carry_insert),
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.carry_blank(1'b0), // 85e
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.carry_blank(at_carry_blank),
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.zero_insert(1'b0), // 85j
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.zero_insert(at_zero_insert),
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.error_reset(oc_err_reset),
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.error_reset(oc_err_reset),
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.quotient_digit_on(1'b0), // 85p
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.quotient_digit_on(1'b0), // 85p
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.overflow_stop_sw(oc_ovflw_stop_sw),
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.overflow_stop_sw(oc_ovflw_stop_sw),
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.overflow_sense_sw(oc_ovflw_sense_sw),
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.overflow_sense_sw(oc_ovflw_sense_sw),
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.mult_div_off(1'b0), // 85k
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.mult_div_off(1'b0), // 85k
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.dist_true_add_gate(1'b0), // 85r
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.dist_true_add_gate(1'b0), // 85r
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.acc_true_add_latch(1'b0), // 85r
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.acc_true_add_latch(at_acc_true_add),
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.shift_overflow(1'b0), // 85b
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.shift_overflow(1'b0), // 85b
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.adder_out(ad_adder_out),
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.adder_out(ad_adder_out),
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.carry_test(ad_carry_test),
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.carry_test(ad_carry_test),
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.no_carry_test(ad_no_carry_test),
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.no_carry_test(ad_no_carry_test),
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.d0l_carry_sig(ad_d0l_carry_sig),
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.d0l_carry_sig(ad_d0l_carry_sig),
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| Line 392... |
Line 399... |
.addr_8003(ar_addr_8003),
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.addr_8003(ar_addr_8003),
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.addr_8002_8003(ar_addr_8002_8003),
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.addr_8002_8003(ar_addr_8002_8003),
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.invalid_addr(ar_invalid_addr)
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.invalid_addr(ar_invalid_addr)
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);
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);
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arith_ctl at (
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.rst(rst),
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.ap(ap),
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.bp(bp),
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.cp(cp),
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.dx(dx),
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.d0(d0),
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.d5(d5),
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.d9(d9),
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.dxl(dxl),
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.d0l(d0l),
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.d1l(d1l),
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.wu(wu),
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.adder_out(ad_adder_out),
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.man_acc_reset(ac_man_acc_reset),
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.overflow_stop(ad_overflow_stop),
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.prog_add_d0(tl_prog_add_d0),
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.half_correct_sig(dc_half_correct_sig),
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.end_of_operation(at_end_of_operation),
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.arith_restart_d5(at_arith_restart_d5),
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.zero_insert(at_zero_insert),
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.carry_blank(at_carry_blank),
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.no_carry_blank(at_no_carry_blank),
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.carry_insert(at_carry_insert),
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.no_carry_insert(at_no_carry_insert),
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.compl_adj(at_compl_adj),
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.divide(at_divide),
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.multiply(at_multiply),
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.acc_true_add(at_acc_true_add),
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.half_correct(at_half_correct),
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.hc_add_5(at_hc_add_5)
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);
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check_acc_tlu ca (
|
check_acc_tlu ca (
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.rst(oc_hard_reset),
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.rst(oc_hard_reset),
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.ap(ap),
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.ap(ap),
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.bp(bp),
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.bp(bp),
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.d0(d0),
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.d0(d0),
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| Line 436... |
Line 476... |
.manual_error_reset_sw(oc_err_reset),
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.manual_error_reset_sw(oc_err_reset),
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.half_or_pgm_stop(oc_half_or_pgm_stop),
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.half_or_pgm_stop(oc_half_or_pgm_stop),
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.prog_restart(ps_restart_sig),
|
.prog_restart(ps_restart_sig),
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.error_stop(es_err_stop),
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.error_stop(es_err_stop),
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.error_sense_restart(es_err_sense_restart),
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.error_sense_restart(es_err_sense_restart),
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.arith_restart(1'b0), // 85d
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.arith_restart(at_arith_restart_d5), // ****
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.stop_code(dc_stop_code),
|
.stop_code(dc_stop_code),
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.code_69(dc_code_69),
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.code_69(dc_code_69),
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.start_10s_60s(dc_turn_on_single_intlk),
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.start_10s_60s(dc_turn_on_single_intlk),
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.end_shift_cntrl(dc_end_shift_control),
|
.end_shift_cntrl(dc_end_shift_control),
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.tlu_on(tl_tlu_on),
|
.tlu_on(tl_tlu_on),
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.end_of_operation(1'b0), // 85d
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.end_of_operation(at_end_of_operation),
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.turn_on_op_intlk(dc_turn_on_op_intlk),
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.turn_on_op_intlk(dc_turn_on_op_intlk),
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.decode_restarts(dc_all_restarts),
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.decode_restarts(dc_all_restarts),
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.use_d_for_i(dc_use_d_for_i),
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.use_d_for_i(dc_use_d_for_i),
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.dist_back_signal(ds_back_sig),
|
.dist_back_signal(ds_back_sig),
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.error_stop_ed0u(es_err_stop_ed0u),
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.error_stop_ed0u(es_err_stop_ed0u),
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| Line 534... |
Line 574... |
.acc_zero_test(zc_acc_zero_test),
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.acc_zero_test(zc_acc_zero_test),
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.acc_no_zero_test(zc_acc_no_zero_test),
|
.acc_no_zero_test(zc_acc_no_zero_test),
|
.acc_plus_test(1'b0), // 85t
|
.acc_plus_test(1'b0), // 85t
|
.acc_minus_test(1'b0), // 85t
|
.acc_minus_test(1'b0), // 85t
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.single_intlk(cc_single_intlk),
|
.single_intlk(cc_single_intlk),
|
.arith_restart(1'b0), // 85d
|
.arith_restart(at_arith_restart_d5), // ****
|
.overflow_sense_sig(ad_overflow_sense_sig),
|
.overflow_sense_sig(ad_overflow_sense_sig),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.all_restarts(dc_all_restarts),
|
.all_restarts(dc_all_restarts),
|
.use_d_for_i(dc_use_d_for_i),
|
.use_d_for_i(dc_use_d_for_i),
|
.turn_on_single_intlk(dc_turn_on_single_intlk),
|
.turn_on_single_intlk(dc_turn_on_single_intlk),
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| Line 776... |
Line 816... |
.s3(s3),
|
.s3(s3),
|
.s4(s4),
|
.s4(s4),
|
.tlu_sig(dc_tlu_sig),
|
.tlu_sig(dc_tlu_sig),
|
.upper_sig(dc_upper_sig),
|
.upper_sig(dc_upper_sig),
|
.lower_sig(dc_lower_sig),
|
.lower_sig(dc_lower_sig),
|
.divide_on(1'b0), // 85p
|
.divide_on(at_divide),
|
.mult_nozero_edxl(1'b0), // 85j
|
.mult_nozero_edxl(1'b0), // 85j
|
.carry_test_latch(ad_carry_test),
|
.carry_test_latch(ad_carry_test),
|
.tlu_or_acc_zero_check(ca_check_latch),
|
.tlu_or_acc_zero_check(ca_check_latch),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.reset_sig(dc_reset_sig),
|
.reset_sig(dc_reset_sig),
|
.no_reset_sig(dc_no_reset_sig),
|
.no_reset_sig(dc_no_reset_sig),
|
.acc_minus_sign(1'b0), // 85t
|
.acc_minus_sign(1'b0), // 85t
|
.compl_adj(1'b0), // 85s
|
.compl_adj(at_compl_adj),
|
.quot_digit_on(1'b0), // 85p
|
.quot_digit_on(1'b0), // 85p
|
.dist_compl_add(1'b0), // 85p
|
.dist_compl_add(1'b0), // 85p
|
.any_left_shift_on(1'b0), // 85j
|
.any_left_shift_on(1'b0), // 85j
|
.right_shift_on(1'b0), // 85a
|
.right_shift_on(1'b0), // 85a
|
.left_shift_on(1'b0), // 85b
|
.left_shift_on(1'b0), // 85b
|
.mult_div_left_shift(1'b0), // 85k
|
.mult_div_left_shift(1'b0), // 85k
|
.sig_digit_on(1'b0), // 85j
|
.sig_digit_on(1'b0), // 85j
|
.hc_add_5(1'b0), // 85a
|
.hc_add_5(at_hc_add_5),
|
.mult_on(1'b0), // 85q
|
.mult_on(at_multiply),
|
.acc_true_add_gate(1'b0), // 85d
|
.acc_true_add_gate(at_acc_true_add),
|
.tlu_on(tl_tlu_on),
|
.tlu_on(tl_tlu_on),
|
.early_dist_zero_entry(tl_early_dist_zero_entry),
|
.early_dist_zero_entry(tl_early_dist_zero_entry),
|
.early_dist_zero_control(tl_early_dist_zero_control),
|
.early_dist_zero_control(tl_early_dist_zero_control),
|
.prog_to_acc_add(tl_prog_to_acc_add),
|
.prog_to_acc_add(tl_prog_to_acc_add),
|
.prog_add(tl_prog_add),
|
.prog_add(tl_prog_add),
|
