| Line 141... |
Line 141... |
// Accumulator and TLU validity checking
|
// Accumulator and TLU validity checking
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire ca_acc_zero, ca_acc_no_zero, ca_check_latch;
|
wire ca_acc_zero, ca_acc_no_zero, ca_check_latch;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
// Control commutator
|
|
//-----------------------------------------------------------------------------
|
|
wire cc_restart_a, cc_restart_b, cc_i_alt, cc_d_alt, cc_man_stop_start,
|
|
cc_run_latch, cc_enable_ri, cc_man_ri_storage, cc_man_ro_storage,
|
|
cc_man_start_ri_dist_latch, cc_i_control_pulse, cc_i_control,
|
|
cc_d_control, cc_d_control_no_8001, cc_start_ri, cc_rips_ri_dist_intlk_a,
|
|
cc_rips_ri_dist_intlk_b, cc_op_intlk, cc_single_intlk, cc_rips,
|
|
cc_ri_dist, cc_acc_to_dist_ri_latch, cc_start_acc_to_dist_ri,
|
|
cc_end_acc_to_dist_ri, cc_rigs, cc_end_rigs;
|
|
|
|
//-----------------------------------------------------------------------------
|
// Register validity checking
|
// Register validity checking
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire ck_error_stop, ck_acc_check_light, ck_prog_check_light,
|
wire ck_error_stop, ck_acc_check_light, ck_prog_check_light,
|
ck_dist_check_light;
|
ck_dist_check_light;
|
|
|
| Line 165... |
Line 176... |
wire ds_back_sig;
|
wire ds_back_sig;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Error stop
|
// Error stop
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire es_err_sense_light, es_err_stop_ed0u, es_err_sense_restart,
|
wire es_err_stop, es_err_sense_light, es_err_stop_ed0u, es_err_sense_restart,
|
es_restart_reset;
|
es_restart_reset;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// General storage
|
// General storage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 190... |
Line 201... |
wire [0:14] oc_gs_ram_addr;
|
wire [0:14] oc_gs_ram_addr;
|
wire oc_read_gs, oc_write_gs;
|
wire oc_read_gs, oc_write_gs;
|
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
|
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
|
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
|
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
|
oc_storage_control, oc_err_restart_sw, oc_ovflw_stop_sw,
|
oc_storage_control, oc_err_restart_sw, oc_ovflw_stop_sw,
|
oc_ovflw_sense_sw;
|
oc_ovflw_sense_sw, oc_pgm_stop_sw;
|
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
|
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
|
oc_hard_reset;
|
oc_hard_reset;
|
wire oc_restart_reset_busy;
|
wire oc_restart_reset_busy;
|
assign display_digit = oc_display_digit;
|
assign display_digit = oc_display_digit;
|
|
|
| Line 208... |
Line 219... |
// Storage select
|
// Storage select
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire [0:6] ss_selected_out;
|
wire [0:6] ss_selected_out;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
// Table look-up
|
|
//-----------------------------------------------------------------------------
|
|
wire tl_tlu_on, tl_early_dist_zero_entry, tl_early_dist_zero_control,
|
|
tl_prog_to_acc_add, tl_prog_add, tl_prog_add_d0, tl_prog_ped_regen,
|
|
tl_tlu_band_change, tl_dist_blank_gate, tl_sel_stor_add_gate,
|
|
tl_ontime_dist_add_gate, tl_upper_lower_check;
|
|
wire [0:9] tl_special_digit;
|
|
|
|
//-----------------------------------------------------------------------------
|
// Translators
|
// Translators
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire tr_gs_write;
|
wire tr_gs_write;
|
wire [0:4] tr_gs_in;
|
wire [0:4] tr_gs_in;
|
wire [0:6] tr_gs_out;
|
wire [0:6] tr_gs_out;
|
| Line 230... |
Line 250... |
.acc_true_add_gate(1'b0), //
|
.acc_true_add_gate(1'b0), //
|
.acc_compl_add_gate(1'b0), //
|
.acc_compl_add_gate(1'b0), //
|
.left_shift_gate(1'b0), //
|
.left_shift_gate(1'b0), //
|
.prog_step_add_gate(1'b0), //
|
.prog_step_add_gate(1'b0), //
|
.shift_num_gate(1'b0), //
|
.shift_num_gate(1'b0), //
|
.select_stor_add_gate(1'b0), //
|
.select_stor_add_gate(tl_sel_stor_add_gate),
|
.adder_entry_a(aa_entry_a)
|
.adder_entry_a(aa_entry_a)
|
);
|
);
|
|
|
add_in_b ab (
|
add_in_b ab (
|
.dist_early_out(ds_early_out),
|
.dist_early_out(ds_early_out),
|
.dist_ontime_out(ds_ontime_out),
|
.dist_ontime_out(ds_ontime_out),
|
.special_int_entry(10'd0), //
|
.special_int_entry(tl_special_digit),
|
.ontime_dist_add_gate_tlu(1'b0), //
|
.ontime_dist_add_gate_tlu(tl_ontime_dist_add_gate),
|
.dist_compl_add_gate(1'b0), //
|
.dist_compl_add_gate(1'b0), //
|
.upper_lower_check(1'b0), //
|
.upper_lower_check(tl_upper_lower_check),
|
.dist_blank_gate(1'b0), //
|
.dist_blank_gate(tl_dist_blank_gate),
|
.early_dist_zero_entry(1'b0), //
|
.early_dist_zero_entry(1'b0), //
|
.dist_true_add_gate(1'b0), //
|
.dist_true_add_gate(1'b0), //
|
.adder_entry_b(ab_entry_b)
|
.adder_entry_b(ab_entry_b)
|
);
|
);
|
|
|
| Line 268... |
Line 288... |
.right_shift_gate(1'b0), //
|
.right_shift_gate(1'b0), //
|
.acc_ri_gate(1'b0), //
|
.acc_ri_gate(1'b0), //
|
.acc_ri_console(oc_acc_ri_console),
|
.acc_ri_console(oc_acc_ri_console),
|
.zero_shift_count(1'b0), //
|
.zero_shift_count(1'b0), //
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.reset_op(1'b0), //
|
.reset_op(dc_reset_sig),
|
.early_idx(early_idx),
|
.early_idx(early_idx),
|
.ontime_idx(ontime_idx),
|
.ontime_idx(ontime_idx),
|
.early_out(ac_early_out),
|
.early_out(ac_early_out),
|
.ontime_out(ac_ontime_out),
|
.ontime_out(ac_ontime_out),
|
.ped_out(ac_ped_out)
|
.ped_out(ac_ped_out)
|
| Line 346... |
Line 366... |
.s1(s1),
|
.s1(s1),
|
.s2(s2),
|
.s2(s2),
|
.s3(s3),
|
.s3(s3),
|
.s4(s4),
|
.s4(s4),
|
.error_reset(oc_err_reset),
|
.error_reset(oc_err_reset),
|
.restart_a(1'b0), //
|
.restart_a(cc_restart_a),
|
.set_8000(oc_set_8000),
|
.set_8000(oc_set_8000),
|
.reset_8000(oc_reset_8000),
|
.reset_8000(oc_reset_8000),
|
.tlu_band_change(1'b0), //
|
.tlu_band_change(tl_tlu_band_change),
|
.double_write(gs_double_write),
|
.double_write(gs_double_write),
|
.no_write(gs_no_write),
|
.no_write(gs_no_write),
|
.bs_to_gs(1'b0), //
|
.bs_to_gs(1'b0), //
|
.ri_gs(1'b0), //
|
.rigs(cc_rigs),
|
.ps_reg_in(ps_ontime_out),
|
.ps_reg_in(ps_ontime_out),
|
.console_in(oc_addr_out),
|
.console_in(oc_addr_out),
|
.ri_addr_reg(op_ri_addr_reg),
|
.ri_addr_reg(op_ri_addr_reg),
|
.console_to_addr_reg(oc_console_to_addr),
|
.console_to_addr_reg(oc_console_to_addr),
|
.addr_th(ar_addr_th),
|
.addr_th(ar_addr_th),
|
| Line 380... |
Line 400... |
.bp(bp),
|
.bp(bp),
|
.d0(d0),
|
.d0(d0),
|
.d2(d2),
|
.d2(d2),
|
.d1_dx(d1_dx),
|
.d1_dx(d1_dx),
|
.acc_ped_out(ac_ped_out),
|
.acc_ped_out(ac_ped_out),
|
.sel_store_add_gate(1'b0), //
|
.sel_store_add_gate(tl_sel_stor_add_gate),
|
.err_reset(oc_err_reset),
|
.err_reset(oc_err_reset),
|
.carry_test_latch(ad_carry_test),
|
.carry_test_latch(ad_carry_test),
|
.no_carry_test_latch(ad_no_carry_test),
|
.no_carry_test_latch(ad_no_carry_test),
|
.acc_zero(ca_acc_zero),
|
.acc_zero(ca_acc_zero),
|
.acc_no_zero(ca_acc_no_zero),
|
.acc_no_zero(ca_acc_no_zero),
|
.check_latch(ca_check_latch)
|
.check_latch(ca_check_latch)
|
);
|
);
|
|
|
|
ctl_commutator cc (
|
|
.rst(oc_hard_reset),
|
|
.ap(ap),
|
|
.bp(bp),
|
|
.cp(cp),
|
|
.dp(dp),
|
|
.dx(dx),
|
|
.d1(d1),
|
|
.d3(d3),
|
|
.d7(d7),
|
|
.d9(d9),
|
|
.d10(d10),
|
|
.dxu(dxu),
|
|
.dxl(dxl),
|
|
.wu(wu),
|
|
.wl(wl),
|
|
.invalid_addr(ar_invalid_addr),
|
|
.man_prog_reset(oc_man_pgm_reset),
|
|
.run_control_sw(oc_run_control),
|
|
.program_start_sw(oc_pgm_start),
|
|
.manual_ri_storage_sw(oc_ri_storage),
|
|
.manual_ro_storage_sw(oc_ro_storage),
|
|
.manual_error_reset_sw(oc_err_reset),
|
|
.half_or_pgm_stop(oc_half_or_pgm_stop),
|
|
.prog_restart(ps_restart_sig),
|
|
.error_stop(es_err_stop),
|
|
.error_sense_restart(es_err_sense_restart),
|
|
.arith_restart(1'b0), //
|
|
.stop_code(dc_stop_code),
|
|
.code_69(dc_code_69),
|
|
.start_10s_60s(dc_turn_on_single_intlk),
|
|
.end_shift_cntrl(1'b0), //
|
|
.tlu_on(tl_tlu_on),
|
|
.end_of_operation(1'b0), //
|
|
.turn_on_op_intlk(dc_turn_on_op_intlk),
|
|
.decode_restarts(dc_all_restarts),
|
|
.use_d_for_i(dc_use_d_for_i),
|
|
.dist_back_signal(ds_back_sig),
|
|
.error_stop_ed0u(es_err_stop_ed0u),
|
|
.divide_overflow_stop(1'b0), //
|
|
.exceed_address_or_stor_select_light(1'b0), //
|
|
.opreg_t(op_opreg_t),
|
|
.opreg_u(op_opreg_u),
|
|
.addr_no_800x(ar_addr_no_800x),
|
|
.addr_8001(ar_addr_8001),
|
|
.dynamic_addr_hit(ar_dynamic_addr_hit),
|
|
.restart_a(cc_restart_a),
|
|
.restart_b(cc_restart_b),
|
|
.i_alt(cc_i_alt),
|
|
.d_alt(cc_d_alt),
|
|
.manual_stop_start(cc_man_stop_start),
|
|
.run_latch(cc_run_latch),
|
|
.enable_ri(cc_enable_ri),
|
|
.manual_ri_storage(cc_man_ri_storage),
|
|
.manual_ro_storage(cc_man_ro_storage),
|
|
.manual_start_ri_dist_latch(cc_man_start_ri_dist_latch),
|
|
.i_control_pulse(cc_i_control_pulse),
|
|
.i_control(cc_i_control),
|
|
.d_control(cc_d_control),
|
|
.d_control_no_8001(cc_d_control_no_8001),
|
|
.start_ri(cc_start_ri),
|
|
.rips_ri_dist_intlk_a(cc_rips_ri_dist_intlk_a),
|
|
.rips_ri_dist_intlk_b(cc_rips_ri_dist_intlk_b),
|
|
.op_intlk(cc_op_intlk),
|
|
.single_intlk(cc_single_intlk),
|
|
.rips(cc_rips),
|
|
.ri_dist(cc_ri_dist),
|
|
.acc_to_dist_ri_latch(cc_acc_to_dist_ri_latch),
|
|
.start_acc_to_dist_ri(cc_start_acc_to_dist_ri),
|
|
.end_acc_to_dist_ri(cc_end_acc_to_dist_ri),
|
|
.rigs(cc_rigs),
|
|
.end_rigs(cc_end_rigs)
|
|
);
|
|
|
checking ck (
|
checking ck (
|
.rst(oc_hard_reset),
|
.rst(oc_hard_reset),
|
.bp(bp),
|
.bp(bp),
|
.d1_dx(d1_dx),
|
.d1_dx(d1_dx),
|
.acc_ontime(ac_ontime_out),
|
.acc_ontime(ac_ontime_out),
|
| Line 403... |
Line 497... |
.error_stop(ck_error_stop),
|
.error_stop(ck_error_stop),
|
.acc_check_light(ck_acc_check_light),
|
.acc_check_light(ck_acc_check_light),
|
.prog_check_light(ck_prog_check_light),
|
.prog_check_light(ck_prog_check_light),
|
.dist_check_light(ck_dist_check_light)
|
.dist_check_light(ck_dist_check_light)
|
);
|
);
|
|
|
decode_ctl dc (
|
decode_ctl dc (
|
.rst(oc_hard_reset),
|
.rst(oc_hard_reset),
|
.ap(ap),
|
.ap(ap),
|
.bp(bp),
|
.bp(bp),
|
.cp(cp),
|
.cp(cp),
|
| Line 429... |
Line 524... |
.d10u(d10u),
|
.d10u(d10u),
|
.opreg_t(op_opreg_t),
|
.opreg_t(op_opreg_t),
|
.opreg_u(op_opreg_u),
|
.opreg_u(op_opreg_u),
|
.addr_u(ar_addr_u),
|
.addr_u(ar_addr_u),
|
.ontime_dist(ds_ontime_out),
|
.ontime_dist(ds_ontime_out),
|
.man_ro_storage(1'b0), //
|
.man_ro_storage(cc_man_ro_storage),
|
.dist_back_sig(ds_back_sig),
|
.dist_back_sig(ds_back_sig),
|
.d_control(1'b0), //
|
.d_control(cc_d_control),
|
.ena_arith_codes(1'b0), //
|
.ena_arith_codes(1'b0), //
|
.pgm_stop_sw(pgm_stop_sw), // ***
|
.pgm_stop_sw(oc_pgm_stop_sw),
|
.acc_zero_test(zc_acc_zero_test),
|
.acc_zero_test(zc_acc_zero_test),
|
.acc_no_zero_test(zc_acc_no_zero_test),
|
.acc_no_zero_test(zc_acc_no_zero_test),
|
.acc_plus_test(1'b0), //
|
.acc_plus_test(1'b0), //
|
.acc_minus_test(1'b0), //
|
.acc_minus_test(1'b0), //
|
.single_intlk(1'b0), //
|
.single_intlk(cc_single_intlk),
|
.arith_restart(1'b0), //
|
.arith_restart(1'b0), //
|
.overflow_sense_sig(ad_overflow_sense_sig),
|
.overflow_sense_sig(ad_overflow_sense_sig),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.all_restarts(dc_all_restarts),
|
.all_restarts(dc_all_restarts),
|
.use_d_for_i(dc_use_d_for_i),
|
.use_d_for_i(dc_use_d_for_i),
|
| Line 475... |
Line 570... |
.dp(dp),
|
.dp(dp),
|
.dx(dx),
|
.dx(dx),
|
.d0(d0),
|
.d0(d0),
|
.d10(d10),
|
.d10(d10),
|
.selected_storage(ss_selected_out),
|
.selected_storage(ss_selected_out),
|
.ri_dist(1'd0), //
|
.ri_dist(cc_ri_dist),
|
.acc_ontime(ac_ontime_out),
|
.acc_ontime(ac_ontime_out),
|
.start_acc_dist_ri(1'd0), //
|
.start_acc_dist_ri(cc_start_acc_to_dist_ri),
|
.end_acc_dist_ri(1'd0),
|
.end_acc_dist_ri(cc_end_acc_to_dist_ri),
|
.acc_dist_ri(1'd0), //
|
.acc_dist_ri(cc_acc_to_dist_ri_latch),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.early_idx(early_idx),
|
.early_idx(early_idx),
|
.ontime_idx(ontime_idx),
|
.ontime_idx(ontime_idx),
|
.ontime_out(ds_ontime_out),
|
.ontime_out(ds_ontime_out),
|
.early_out(ds_early_out),
|
.early_out(ds_early_out),
|
| Line 501... |
Line 596... |
.err_reset(oc_err_reset),
|
.err_reset(oc_err_reset),
|
.err_sense_reset(oc_err_sense_reset),
|
.err_sense_reset(oc_err_sense_reset),
|
.clock_err_sig(1'b0), //
|
.clock_err_sig(1'b0), //
|
.err_stop_sig(ck_error_stop),
|
.err_stop_sig(ck_error_stop),
|
.restart_reset_busy(oc_restart_reset_busy),
|
.restart_reset_busy(oc_restart_reset_busy),
|
|
.err_stop(es_err_stop),
|
.err_sense_light(es_err_sense_light),
|
.err_sense_light(es_err_sense_light),
|
.err_stop_ed0u(es_err_stop_ed0u),
|
.err_stop_ed0u(es_err_stop_ed0u),
|
.err_sense_restart(es_err_sense_restart),
|
.err_sense_restart(es_err_sense_restart),
|
.restart_reset(es_restart_reset)
|
.restart_reset(es_restart_reset)
|
);
|
);
|
| Line 574... |
Line 670... |
.ro_storage(oc_ro_storage),
|
.ro_storage(oc_ro_storage),
|
.storage_control(oc_storage_control),
|
.storage_control(oc_storage_control),
|
.err_restart_sw(oc_err_restart_sw),
|
.err_restart_sw(oc_err_restart_sw),
|
.ovflw_stop_sw(oc_ovflw_stop_sw),
|
.ovflw_stop_sw(oc_ovflw_stop_sw),
|
.ovflw_sense_sw(oc_ovflw_sense_sw),
|
.ovflw_sense_sw(oc_ovflw_sense_sw),
|
|
.pgm_stop_sw(oc_pgm_stop_sw),
|
.man_pgm_reset(oc_man_pgm_reset),
|
.man_pgm_reset(oc_man_pgm_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.set_8000(oc_set_8000),
|
.set_8000(oc_set_8000),
|
.reset_8000(oc_reset_8000),
|
.reset_8000(oc_reset_8000),
|
.hard_reset(oc_hard_reset),
|
.hard_reset(oc_hard_reset),
|
| Line 596... |
Line 693... |
.d0(d0),
|
.d0(d0),
|
.d9(d9),
|
.d9(d9),
|
.d10(d10),
|
.d10(d10),
|
.d1_d5(d1_d5),
|
.d1_d5(d1_d5),
|
.d5_dx(d5_dx),
|
.d5_dx(d5_dx),
|
.restart_a(1'b0), //
|
.restart_a(cc_restart_a),
|
.restart_b(1'b0), //
|
.restart_b(cc_restart_b),
|
.d_alt(1'b0), //
|
.d_alt(cc_d_alt),
|
.i_alt(1'b0), //
|
.i_alt(cc_i_alt),
|
.tlu_band_change(1'b0), //
|
.tlu_band_change(tl_tlu_band_change),
|
.man_prog_reset(oc_man_pgm_reset),
|
.man_prog_reset(oc_man_pgm_reset),
|
.prog_step_ped(ps_ped_out),
|
.prog_step_ped(ps_ped_out),
|
.opreg_t(op_opreg_t),
|
.opreg_t(op_opreg_t),
|
.opreg_u(op_opreg_u),
|
.opreg_u(op_opreg_u),
|
.ri_addr_reg(op_ri_addr_reg)
|
.ri_addr_reg(op_ri_addr_reg)
|
| Line 618... |
Line 715... |
.d0(d0),
|
.d0(d0),
|
.d10(d10),
|
.d10(d10),
|
.early_idx(early_idx),
|
.early_idx(early_idx),
|
.ontime_idx(ontime_idx),
|
.ontime_idx(ontime_idx),
|
.man_prog_reset(oc_man_pgm_reset),
|
.man_prog_reset(oc_man_pgm_reset),
|
.rips(1'b0), //
|
.rips(cc_rips),
|
.adder_out(ad_adder_out),
|
.adder_out(ad_adder_out),
|
.sel_store_out(ss_selected_out),
|
.sel_store_out(ss_selected_out),
|
.prog_ped_regen(1'b1), //
|
.prog_ped_regen(tl_prog_ped_regen),
|
.prog_add(1'b0), //
|
.prog_add(tl_prog_add),
|
.early_out(ps_early_out),
|
.early_out(ps_early_out),
|
.ontime_out(ps_ontime_out),
|
.ontime_out(ps_ontime_out),
|
.ped_out(ps_ped_out),
|
.ped_out(ps_ped_out),
|
.prog_restart_sig(ps_restart_sig)
|
.prog_restart_sig(ps_restart_sig)
|
);
|
);
|
| Line 636... |
Line 733... |
.d1_dx(d1_dx),
|
.d1_dx(d1_dx),
|
.addr_no_800x(ar_addr_no_800x),
|
.addr_no_800x(ar_addr_no_800x),
|
.addr_8000(ar_addr_8000),
|
.addr_8000(ar_addr_8000),
|
.addr_8001(ar_addr_8001),
|
.addr_8001(ar_addr_8001),
|
.addr_8002_8003(ar_addr_8002_8003),
|
.addr_8002_8003(ar_addr_8002_8003),
|
.addr_hot_8000(1'b0), //
|
.addr_hot_8000(1'b0), // *** see cc
|
.acc_ontime(ac_ontime_out),
|
.acc_ontime(ac_ontime_out),
|
.dist_ontime(ds_ontime_out),
|
.dist_ontime(ds_ontime_out),
|
.gs_out(tr_gs_out),
|
.gs_out(tr_gs_out),
|
.console_switches(oc_data_out),
|
.console_switches(oc_data_out),
|
.acc_plus(1'b0), //
|
.acc_plus(1'b0), //
|
.acc_minus(1'b0), //
|
.acc_minus(1'b0), //
|
.selected_out(ss_selected_out)
|
.selected_out(ss_selected_out)
|
);
|
);
|
|
|
|
tlu tl (
|
|
.rst(oc_hard_reset),
|
|
.ap(ap),
|
|
.bp(bp),
|
|
.dx(dx),
|
|
.d0(d0),
|
|
.d4(d4),
|
|
.d5(d5),
|
|
.d10(d10),
|
|
.dxl(dxl),
|
|
.d0l(d0l),
|
|
.d10u(d10u),
|
|
.w0(w0),
|
|
.w1(w1),
|
|
.w2(w2),
|
|
.w3(w3),
|
|
.w4(w4),
|
|
.w5(w5),
|
|
.w6(w6),
|
|
.w7(w7),
|
|
.w8(w8),
|
|
.w9(w9),
|
|
.wl(wl),
|
|
.wu(wu),
|
|
.s0(s0),
|
|
.s1(s1),
|
|
.s2(s2),
|
|
.s3(s3),
|
|
.s4(s4),
|
|
.tlu_sig(dc_tlu_sig),
|
|
.upper_sig(dc_upper_sig),
|
|
.lower_sig(dc_lower_sig),
|
|
.divide_on(1'b0), //
|
|
.mult_nozero_edxl(1'b0), //
|
|
.carry_test_latch(ad_carry_test),
|
|
.tlu_or_acc_zero_check(ca_check_latch),
|
|
.man_acc_reset(oc_man_acc_reset),
|
|
.reset_sig(dc_reset_sig),
|
|
.no_reset_sig(dc_no_reset_sig),
|
|
.acc_minus_sign(1'b0), //
|
|
.compl_adj(1'b0), //
|
|
.quot_digit_on(1'b0), //
|
|
.dist_compl_add(1'b0), //
|
|
.any_left_shift_on(1'b0), //
|
|
.right_shift_on(1'b0), //
|
|
.left_shift_on(1'b0), //
|
|
.mult_div_left_shift(1'b0), //
|
|
.sig_digit_on(1'b0), //
|
|
.hc_add_5(1'b0), //
|
|
.mult_on(1'b0), //
|
|
.acc_true_add_gate(1'b0), //
|
|
.tlu_on(tl_tlu_on),
|
|
.early_dist_zero_entry(tl_early_dist_zero_entry),
|
|
.early_dist_zero_control(tl_early_dist_zero_control),
|
|
.prog_to_acc_add(tl_prog_to_acc_add),
|
|
.prog_add(tl_prog_add),
|
|
.prog_add_d0(tl_prog_add_d0),
|
|
.prog_ped_regen(tl_prog_ped_regen),
|
|
.special_digit(tl_special_digit),
|
|
.tlu_band_change(tl_tlu_band_change),
|
|
.dist_blank_gate(tl_dist_blank_gate),
|
|
.sel_stor_add_gate(tl_sel_stor_add_gate),
|
|
.ontime_dist_add_gate(tl_ontime_dist_add_gate),
|
|
.upper_lower_check(tl_upper_lower_check)
|
|
);
|
|
|
translators tr (
|
translators tr (
|
.dist_early_out(`biq_blank),
|
.dist_early_out(`biq_blank),
|
.bs_out(`biq_blank),
|
.bs_out(`biq_blank),
|
.console_out(oc_console_out),
|
.console_out(oc_console_out),
|
.ri_gs(1'b0), //
|
.ri_gs(cc_rigs),
|
.ri_bs(1'b0), //
|
.ri_bs(1'b0), //
|
.ri_console(oc_write_gs),
|
.ri_console(oc_write_gs),
|
.n800x(ar_addr_no_800x),
|
.n800x(ar_addr_no_800x),
|
.console_read_gs(oc_read_gs),
|
.console_read_gs(oc_read_gs),
|
.gs_out(gs_out),
|
.gs_out(gs_out),
|
