| Line 5... |
Line 5... |
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
|
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
|
// http:////www.opencores.org/project,i650
|
// http:////www.opencores.org/project,i650
|
//
|
//
|
// Description: Drum code translators.
|
// Description: Drum code translators.
|
//
|
//
|
// Additional Comments:
|
// Additional Comments: See US 2959351, Fig. 72.
|
//
|
//
|
// Copyright (c) 2015 Robert Abeles
|
// Copyright (c) 2015 Robert Abeles
|
//
|
//
|
// This source file is free software; you can redistribute it
|
// This source file is free software; you can redistribute it
|
// and/or modify it under the terms of the GNU Lesser General
|
// and/or modify it under the terms of the GNU Lesser General
|
| Line 30... |
Line 30... |
`include "defines.v"
|
`include "defines.v"
|
|
|
module translators (
|
module translators (
|
input [0:6] dist_early_out, bs_out, console_out,
|
input [0:6] dist_early_out, bs_out, console_out,
|
input ri_gs, ri_bs, ri_console,
|
input ri_gs, ri_bs, ri_console,
|
input n800x,
|
input n800x, console_read_gs,
|
input [0:4] gs_out,
|
input [0:4] gs_out,
|
output gs_write,
|
output gs_write,
|
output [0:4] gs_in,
|
output [0:4] gs_in,
|
output reg[0:6] select_out
|
output reg[0:6] gs_biq_out
|
);
|
);
|
|
|
reg [0:6] sel_in7;
|
reg [0:6] sel_in7;
|
wire [0:6] sel_out7;
|
wire [0:6] sel_out7;
|
xlate7to5 x75 (sel_in7, gs_in);
|
xlate7to5 x75 (sel_in7, gs_in);
|
| Line 49... |
Line 49... |
always @(*) begin
|
always @(*) begin
|
sel_in7 = ri_console? console_out
|
sel_in7 = ri_console? console_out
|
: ri_gs? dist_early_out
|
: ri_gs? dist_early_out
|
: ri_bs? bs_out
|
: ri_bs? bs_out
|
: `biq_blank;
|
: `biq_blank;
|
select_out = (n800x)? sel_out7 : `biq_blank;
|
gs_biq_out = (n800x | console_read_gs)? sel_out7 : `biq_blank;
|
end;
|
end;
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
