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[/] [iicmb/] [trunk/] [src/] [avalon_mm.vhd] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 49... Line 49...
    clk           : in    std_logic;                                -- Clock input
    clk           : in    std_logic;                                -- Clock input
    s_rst         : in    std_logic;                                -- Synchronous reset (active high)
    s_rst         : in    std_logic;                                -- Synchronous reset (active high)
    ------------------------------------
    ------------------------------------
    ------------------------------------
    ------------------------------------
    -- Avalon-MM slave interface:
    -- Avalon-MM slave interface:
    waitrequest   :   out std_logic;
    waitrequest   :   out std_logic;                            -- Wait request
    readdata      :   out std_logic_vector(31 downto 0);
    readdata      :   out std_logic_vector(31 downto 0);        -- Data from slave to master
    readdatavalid :   out std_logic;
    readdatavalid :   out std_logic;                            -- Data validity indication
    writedata     : in    std_logic_vector(31 downto 0);
    writedata     : in    std_logic_vector(31 downto 0);        -- Data from master to slave
    write         : in    std_logic;
    write         : in    std_logic;                            -- Asserted to indicate write transfer
    read          : in    std_logic;
    read          : in    std_logic;                            -- Asserted to indicate read transfer
    byteenable    : in    std_logic_vector( 3 downto 0);
    byteenable    : in    std_logic_vector( 3 downto 0);        -- Enables specific byte lane(s)
    ------------------------------------
    ------------------------------------
    ------------------------------------
    ------------------------------------
    -- Regblock interface:
    -- Regblock interface:
    wr            :   out std_logic_vector( 3 downto 0);            -- Write (active high)
    wr            :   out std_logic_vector( 3 downto 0);            -- Write (active high)
    rd            :   out std_logic_vector( 3 downto 0);            -- Read (active high)
    rd            :   out std_logic_vector( 3 downto 0);            -- Read (active high)
    idata         :   out std_logic_vector(31 downto 0);            -- Data from System Bus
    idata         :   out std_logic_vector(31 downto 0);            -- Data from System Bus
    odata         : in    std_logic_vector(31 downto 0)             -- Data to System Bus
    odata         : in    std_logic_vector(31 downto 0)         -- Data for System Bus
    ------------------------------------
    ------------------------------------
  );
  );
end entity avalon_mm;
end entity avalon_mm;
--==============================================================================
--==============================================================================
 
 

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