URL https://opencores.org/ocsvn/iicmb/iicmb/trunk

Subversion Repositories iicmb

[/] [iicmb/] [trunk/] [src/] [wishbone.vhd] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 49...	Line 49...
`clk_i : in std_logic; -- Clock input`	`clk_i : in std_logic; -- Clock input`
`rst_i : in std_logic; -- Synchronous reset (active high)`	`rst_i : in std_logic; -- Synchronous reset (active high)`
`------------------------------------`	`------------------------------------`
`------------------------------------`	`------------------------------------`
`-- Wishbone slave interface:`	`-- Wishbone slave interface:`
`cyc_i : in std_logic; --`	`cyc_i : in std_logic; -- Valid bus cycle indication`
`stb_i : in std_logic; --`	`stb_i : in std_logic; -- Slave selection`
`ack_o : out std_logic; --`	`ack_o : out std_logic; -- Acknowledge output`
`adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address`	`adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address`
`we_i : in std_logic; --`	`we_i : in std_logic; -- Write enable`
`dat_i : in std_logic_vector( 7 downto 0); -- Data input`	`dat_i : in std_logic_vector( 7 downto 0); -- Data input`
`dat_o : out std_logic_vector( 7 downto 0); -- Data output`	`dat_o : out std_logic_vector( 7 downto 0); -- Data output`
`------------------------------------`	`------------------------------------`
`------------------------------------`	`------------------------------------`
`-- Regblock interface:`	`-- Regblock interface:`