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----------------------------------------------------------------------------------
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-- Company: VISENGI S.L. (www.visengi.com)
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-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
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--
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-- Create Date: 19:34:36 04/November/2008
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-- Project Name: IMA ADPCM Encoder
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-- Tool versions: Xilinx ISE 9.2i
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-- Description:
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--
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-- Description: This project features a full-hardware sound compressor using the well known algorithm IMA ADPCM.
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-- The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player
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-- with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes
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-- an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file.
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-- Compression ratio is fixed for IMA-ADPCM, being 4:1.
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--
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--
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-- LICENSE TERMS: GNU GENERAL PUBLIC LICENSE Version 3
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--
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-- That is you may use it only in NON-COMMERCIAL projects.
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-- You are only required to include in the copyrights/about section
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-- that your system contains a "IMA ADPCM Encoder (C) VISENGI S.L. under GPL license"
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-- This holds also in the case where you modify the core, as the resulting core
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-- would be a derived work.
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-- Also, we would like to know if you use this core in a project of yours, just an email will do.
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--
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-- Please take good note of the disclaimer section of the GPL license, as we don't
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-- take any responsability for anything that this core does.
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----------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- WAV HEADER ROM
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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entity WAV_header_rom is
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generic (ROMADDR_W : integer := 6;
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ROMDATA_W : integer := 8);
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port(
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addr0 : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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clk : in STD_LOGIC;
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datao0 : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0));
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end WAV_header_rom;
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architecture RTL of WAV_header_rom is
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type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
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of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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constant rom : ROM_TYPE :=
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(
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-- Everything little endian:
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-- 52 49 46 46 00 00 00 00 57 41 56 45 66 6D 74 20 14 00 00 00
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-- R I F F x x x x W A V E f m t x x x x <-- these last are ok
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--x ^ ^ ^ ^ = change these for (file_size-8 or, simply, bytes that follow)
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-- 11 00 <-- wFormatTag = IMA ADPCM
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-- 01 00 <-- nChannels = 1 (Mono)
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--x40 1F 00 00 <-- nSamplesPerSec = 8000
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--xD7 0F 00 00 <-- nAvgBytesPerSec = 4055
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-- (505 samples/block -> 8000 samples/sec -> 504/2 + 4 header bytes w. 1 sample = 256 bytes/block -> (8000/505)*256 = 4055 bytes/sec)
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-- can be an approximate number and still be reproducible (i.e. nAvgBytesPerSec=nSamplesPerSec/512*256=nSamplesPerSec/2)
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-- 00 01 <-- nBlockAlign = 100h = 256 bytes block size
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-- 04 00 <-- wBitsPerSample = 4 bits
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-- 02 00 <-- cbSize = size of extension = 2 bytes
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-- F9 01 <-- wSamplesPerBlock = 505 samples/block
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--
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-- 66 61 63 74 04 00 00 00 00 00 00 00 64 61 74 61 00 00 00 00
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--x f a c t x x x x x x x x d a t a x x x x <-- change these for (file_size-60 or, simply, bytes that follow)
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--x ^ ^ ^ ^ = # samples per channel in file
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"01010010",
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"01001001",
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"01000110",
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"01000110",
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"11111111",
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"11111111",
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"11111111",
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"01111111",
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"01010111",
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"01000001",
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"01010110",
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"01000101",
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"01100110",
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"01101101",
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"01110100",
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"00100000",
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"00010100",
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"00000000",
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"00000000",
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"00000000",
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"00010001",
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"00000000",
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"00000001",
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"00000000",
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"01000000",
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"00011111",
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"00000000",
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"00000000",
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"11010111",
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"00001111",
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"00000000",
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"00000000",
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"00000000",
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"00000001",
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"00000100",
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"00000000",
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"00000010",
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"00000000",
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"11111001",
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"00000001",
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"01100110",
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"01100001",
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"01100011",
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"01110100",
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"00000100",
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"00000000",
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"00000000",
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"00000000",
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"11111111",
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"11111111",
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"11111111",
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"01111111",
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"01100100",
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"01100001",
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"01110100",
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"01100001",
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"11111111",
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"11111111",
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"11111111",
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"01111111",
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--0 stuffing
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"00000000",
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"00000000",
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"00000000",
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"00000000");
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signal addr_reg0 : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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datao0 <= rom( TO_INTEGER(UNSIGNED(addr_reg0)) );
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process(clk)
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begin
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if clk = '1' and clk'event then
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addr_reg0 <= addr0;
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end if;
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end process;
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end RTL;
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No newline at end of file
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No newline at end of file
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