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https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module accumulatorMUX (accMuxSel, immData, aluOut, accMuxOut);
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module accumulatorMUX (accMuxSel, immData, aluOut
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`ifdef timerAndCounter_peripheral
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, tcLoadIn, tcAccIn
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`endif
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`ifdef UART_peripheral
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, uartDataIn
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`endif
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`ifdef SPI_peripheral
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, spiStatIn, spiBufIn
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`endif
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, accMuxOut
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);
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input [`accMuxSelLen-1:0] accMuxSel;
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input [`accMuxSelLen-1:0] accMuxSel;
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input [`immDataLen-1:0] immData;
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input [`immDataLen-1:0] immData;
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input [7:0] aluOut;
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input [7:0] aluOut;
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`ifdef timerAndCounter_peripheral
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input [7:0] tcLoadIn, tcAccIn;
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`endif
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`ifdef UART_peripheral
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input [7:0] uartDataIn;
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`endif
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`ifdef SPI_peripheral
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input [7:0] spiStatIn, spiBufIn;
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`endif
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output [7:0] accMuxOut;
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output [7:0] accMuxOut;
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reg [7:0] accMuxOut;
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reg [7:0] accMuxOut;
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always @ *
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always @ *
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begin
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begin
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case (accMuxSel)
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case (accMuxSel)
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`accMuxSel0 : begin
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`accMuxSelImmData : begin
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accMuxOut = immData;
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accMuxOut = immData;
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end
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end
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`accMuxSel1 : begin
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`accMuxSelAluOut : begin
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accMuxOut = aluOut;
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accMuxOut = aluOut;
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end
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end
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`ifdef timerAndCounter_peripheral
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`accMuxSelTcLoad : begin
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accMuxOut = tcLoadIn;
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end
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`accMuxSelTcAcc : begin
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accMuxOut = tcAccIn;
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end
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`endif
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`ifdef UART_peripheral
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`accMuxSelUart : begin
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accMuxOut = uartDataIn;
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end
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`endif
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`ifdef SPI_peripheral
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`accMuxSelSpiStat : begin
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accMuxOut = spiStatIn;
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end
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`accMuxSelSpiBuf : begin
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accMuxOut = spiBufIn;
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end
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`endif
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default : begin
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default : begin
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accMuxOut = 8'bzzzzzzzz;
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accMuxOut = 8'bzzzzzzzz;
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end
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end
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endcase
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endcase
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