URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [accMUX.v] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 6...	Line 6...
`module accumulatorMUX (accMuxSel, immData, aluOut`	`module accumulatorMUX (accMuxSel, immData, aluOut`
`ifdef timerAndCounter_peripheral	`ifdef timerAndCounter_peripheral
`, tcLoadIn, tcAccIn`	`, tcLoadIn, tcAccIn`
`endif	`endif
`ifdef UART_peripheral	`ifdef UART_peripheral
`, uartDataIn`	`, uartDataIn, uartStatIn`
`endif	`endif
`ifdef SPI_peripheral	`ifdef SPI_peripheral
`, spiStatIn, spiBufIn`	`, spiStatIn, spiBufIn`
`endif	`endif
`, accMuxOut`	`, accMuxOut`
Line 21...	Line 21...
`input [7:0] aluOut;`	`input [7:0] aluOut;`
`ifdef timerAndCounter_peripheral	`ifdef timerAndCounter_peripheral
`input [7:0] tcLoadIn, tcAccIn;`	`input [7:0] tcLoadIn, tcAccIn;`
`endif	`endif
`ifdef UART_peripheral	`ifdef UART_peripheral
`input [7:0] uartDataIn;`	`input [7:0] uartDataIn, uartStatIn;`
`endif	`endif
`ifdef SPI_peripheral	`ifdef SPI_peripheral
`input [7:0] spiStatIn, spiBufIn;`	`input [7:0] spiStatIn, spiBufIn;`
`endif	`endif

Line 56...	Line 56...
`accMuxOut = tcAccIn;`	`accMuxOut = tcAccIn;`
`end`	`end`
`endif	`endif

`ifdef UART_peripheral	`ifdef UART_peripheral
`accMuxSelUart : begin	`accMuxSelUartData : begin
`accMuxOut = uartDataIn;`	`accMuxOut = uartDataIn;`
`end`	`end`

	`accMuxSelUartStat : begin
	`accMuxOut = uartStatIn;`
	`end`
`endif	`endif

`ifdef SPI_peripheral	`ifdef SPI_peripheral
`accMuxSelSpiStat : begin	`accMuxSelSpiStat : begin
`accMuxOut = spiStatIn;`	`accMuxOut = spiStatIn;`