URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [alu.v] - Diff between revs 5 and 6

Rev 5	Rev 6
Line 1...	Line 1...

`include "timescale.v"	`include "timescale.v"
`include "defines.v"	`include "defines.v"

module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2,	module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
`output [7:0] aluOut, output carryOut);`	`output [7:0] aluOut, output carryOut);`


`wire [8:0] operand1 = {1'b0, op1};`	`wire [8:0] operand1 = {1'b0, op1};`
`wire [8:0] operand2 = {1'b0, op2};`	`wire [8:0] operand2 = {1'b0, op2};`
Line 17...	Line 17...

`always @ (op1 or op2 or aluOpcode)`	`always @ (op1 or op2 or aluOpcode)`
`begin`	`begin`


	`if (aluEn)`
	`begin`

`case (aluOpcode)`	`case (aluOpcode)`

`AND_alu : begin	`AND_alu : begin
`aluOutput = op1 & op2;`	`aluOutput = op1 & op2;`
Line 73...	Line 75...
`$write ("Unknown operation. \nmodule : ALU");`	`$write ("Unknown operation. \nmodule : ALU");`
`end`	`end`
`endcase`	`endcase`

`end`	`end`
	`else`
	`begin`

	`aluOutput = aluOutput;`
	`end`

	`end`

`assign aluOut = aluOutput;`	`assign aluOut = aluOutput;`
`assign carryOut = carryOutput;`	`assign carryOut = carryOutput;`

`endmodule`	`endmodule`