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https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
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Rev 9 |
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Line 10... |
wire [8:0] operand2 = {1'b0, op2};
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wire [8:0] operand2 = {1'b0, op2};
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wire [8:0] addRes = operand1 + operand2;
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wire [8:0] addRes = operand1 + operand2;
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wire [8:0] subRes = operand1 - operand2;
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wire [8:0] subRes = operand1 - operand2;
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reg [8:0] aluOutput;
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reg [8:0] aluOut = 0;
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reg carryOutput;
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reg carryOut = 0;
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always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
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always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
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begin
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begin
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begin
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begin
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case (aluOpcode)
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case (aluOpcode)
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`AND_alu : begin
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`AND_alu : begin
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aluOutput = op1 & op2;
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aluOut = op1 & op2;
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end
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end
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`OR_alu : begin
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`OR_alu : begin
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aluOutput = op1 | op2;
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aluOut = op1 | op2;
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end
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end
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`XOR_alu : begin
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`XOR_alu : begin
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aluOutput = op1^op2;
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aluOut = op1^op2;
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end
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end
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`GT_alu : begin
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`GT_alu : begin
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aluOutput = op1>op2 ? 1'b1 : 1'b0;
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aluOut = op1>op2 ? 1'b1 : 1'b0;
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end
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end
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`GE_alu : begin
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`GE_alu : begin
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aluOutput = op1>=op2 ? 1'b1 : 1'b0;
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aluOut = op1>=op2 ? 1'b1 : 1'b0;
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end
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end
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`EQ_alu : begin
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`EQ_alu : begin
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aluOutput = op1==op2 ? 1'b1 : 1'b0;
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aluOut = op1==op2 ? 1'b1 : 1'b0;
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end
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end
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`LE_alu : begin
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`LE_alu : begin
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aluOutput = op1<=op2 ? 1'b1 : 1'b0;
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aluOut = op1<=op2 ? 1'b1 : 1'b0;
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end
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end
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`LT_alu : begin
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`LT_alu : begin
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aluOutput = op1<op2 ? 1'b1 : 1'b0;
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aluOut = op1<op2 ? 1'b1 : 1'b0;
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end
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end
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`ADD_alu : begin
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`ADD_alu : begin
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aluOutput = addRes[7:0];
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aluOut = addRes[7:0];
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carryOutput = addRes[8];
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carryOut = addRes[8];
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end
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end
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`SUB_alu : begin
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`SUB_alu : begin
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aluOutput = subRes[7:0];
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aluOut = subRes[7:0];
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carryOutput = subRes[8];
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carryOut = subRes[8];
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end
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end
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`LD_data : begin
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`LD_data : begin
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aluOutput = op1;
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aluOut = op2;
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end
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end
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default : begin
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default : begin
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aluOutput = 16'b0;
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aluOut = 16'b0;
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$write ("\nUnknown operation. \tmodule : ALU");
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$write ("\nUnknown operation. \tmodule : ALU");
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end
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end
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endcase
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endcase
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end
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end
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else
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else
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begin
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begin
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aluOutput = aluOutput;
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aluOut = aluOut;
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end
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end
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end
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end
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assign aluOut = aluOutput;
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assign carryOut = carryOutput;
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endmodule
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endmodule
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