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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module controlUnit (clk, reset, instOpCodeIn, acc0, iomemCode,
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module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
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branch,
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branch,
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accMuxSel, accEn, op2MuxSel, aluOpcode,
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accMuxSel, accEn, op2MuxSel, aluOpcode,
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bitRamEn, bitRamRw, byteRamEn, byteRamRw,
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bitRamEn, bitRamRw, byteRamEn, byteRamRw,
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inputRead, outputRw
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inputRead, outputRw
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output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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output inputRead, outputRw;
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output inputRead, outputRw;
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
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output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
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`endif;
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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output uartRead, uartWrite;
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output uartRead, uartWrite;
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
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output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
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`endif
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`endif
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reg branch;
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reg [`accMuxSelLen-1:0] accMuxSel;
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reg accEn;
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reg [`op2MuxSelLen-1:0] op2MuxSel;
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reg [`aluOpcodeLen-1:0] aluOpcode;
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reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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reg inputRead, outputRw;
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`ifdef timerAndCounter_peripheral
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reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
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`endif
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`ifdef UART_peripheral
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reg uartRead, uartWrite;
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`endif
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`ifdef SPI_peripheral
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reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
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`endif
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reg [`cuStateLen-1:0] state;
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// control unit FSM states:
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parameter s = `cuStateLen'b0;
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parameter sTc = `cuStateLen'b1;
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parameter sBr = `cuStateLen'b10;
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parameter sLd = `cuStateLen'b11;
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parameter sSt = `cuStateLen'b100;
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parameter sUart = `cuStateLen'b101;
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parameter sSpi = `cuStateLen'b110;
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parameter sAlu = `cuStateLen'b111;
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always @ (negedge clk)
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begin
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if (reset)
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begin
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state = s;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluOpcode = 0; bitRamEn = 0;
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bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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else
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begin
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// execution unit control signals
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case (state)
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s : begin
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case (instOpCode)
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`END : begin
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state = sBr;
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branch = 1; // branch to some address . . .
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accMuxSel = 0;
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accEn = 0;
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op2MuxSel = 0;
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aluOpcode = 0;
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bitRamEn = 0;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamRw = 1;
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inputRead = 0;
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outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0;
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spiBufShift = 0;
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`endif
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end // end case END
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`JMP : begin
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state = sBr;
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branch = 1; // branch to some address . . .
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accMuxSel = 0;
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accEn = 0;
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op2MuxSel = 0;
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aluOpcode = 0;
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bitRamEn = 0;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamRw = 1;
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inputRead = 0;
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outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end // end case JMP
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`Ld : begin
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// load thr. op2 MUX and alu.... enable acc in next cycle
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state = sLd;
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branch = 0;
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accMuxSel = 0;
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accEn = 0;
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case (iomemCode)
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2'b00 : op2MuxSel = `op2MuxSelInput;
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2'b01 : op2MuxSel = `op2MuxSelOutput;
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2'b10 : op2MuxSel = `op2MuxSelBitRam;
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2'b11 : op2MuxSel = `op2MuxSelByteRam;
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default: op2MuxSel = `op2MuxSelInput;
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endcase
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aluOpcode = `LD_data;
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bitRamEn = 0;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamRw = 1;
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inputRead = 0;
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outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end // end case Ld
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`Ldi : begin
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state = sAlu;
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branch = 0;
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accMuxSel = `accMuxSelImmData; // select imm data thr mux
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accEn = 1; // acc enabled
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op2MuxSel = 0;
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aluOpcode = 0;
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bitRamEn = 0;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamRw = 1;
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inputRead = 0;
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outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end // end case Ldi
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`ST : begin
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state = sSt;
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branch = 0;
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accMuxSel = 0;
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accEn = 0;
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op2MuxSel = 0;
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aluOpcode = 0;
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bitRamRw = 0;
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byteRamRw = 0;
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inputRead = 0;
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case (iomemCode)
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2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; end
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2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; end
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2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
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default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
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endcase
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`ADD : begin
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state = sAlu;
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aluOpcode = `ADD_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`SUB : begin
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state = sAlu;
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aluOpcode = `SUB_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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// MUL & DIV are not implemented
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`AND : begin
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state = sAlu;
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aluOpcode = `AND_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`OR : begin
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state = sAlu;
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aluOpcode = `OR_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`XOR : begin
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state = sAlu;
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aluOpcode = `XOR_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`GrT : begin
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state = sAlu;
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aluOpcode = `GT_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`GE : begin
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state = sAlu;
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aluOpcode = `GE_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`EQ : begin
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state = sAlu;
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aluOpcode = `EQ_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`LE : begin
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state = sAlu;
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aluOpcode = `LE_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`LT : begin
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state = sAlu;
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aluOpcode = `LT_alu;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`ifdef timeAndCounter_peripheral
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`PRE : begin
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state = sTc;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
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aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef UART_peripheral
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uartRead = 0; uartWrite = 0;
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`endif
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`ifdef SPI_peripheral
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sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
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`endif
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end
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`endif
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`ifdef timeAndCounter_peripheral
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`ETY : begin
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state = sTc;
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|
|
|
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
|
`RST : begin
|
|
state = sTc;
|
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
|
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
|
`LdTC : begin
|
|
state = sTc;
|
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;
|
|
|
|
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
|
|
|
|
aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
|
`LdACC : begin
|
|
state = sTc;
|
|
|
|
entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
|
|
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
|
|
|
|
aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
`UARTrd : begin
|
|
state = sUart;
|
|
|
|
uartRead = 1; uartWrite = 0;
|
|
|
|
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
|
|
|
|
aluOpcode = 0; branch = 0;op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
`endif
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
`UARTwr : begin
|
|
state = sUart;
|
|
|
|
uartRead = 0; uartWrite = 1;
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
`endif
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
`SPIxFER : begin
|
|
state = sSpi;
|
|
|
|
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
`endif
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
`SPIstat : begin
|
|
state = sSpi;
|
|
|
|
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
`endif
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
`SPIwBUF : begin
|
|
state = sSpi;
|
|
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
|
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
`endif
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
`SPIrBUF : begin
|
|
state = sSpi;
|
|
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
|
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
`endif
|
|
|
|
`ifdef UART_peripheral
|
|
uartRead = 0; uartWrite = 0;
|
|
`endif
|
|
|
|
end
|
|
`endif
|
|
|
|
default : begin
|
|
|
|
$write (" unknown/unused instruction op-code encountered by control unit ");
|
|
$stop;
|
|
end
|
|
endcase // end case (instOpCode)
|
|
|
|
|
|
|
|
end // end case (s)
|
|
|
|
|
|
sBr : begin
|
|
branch = 0;
|
|
state = s;
|
|
end // end case sBr
|
|
|
|
|
|
sLd : begin
|
|
accEn = 0;
|
|
state = s;
|
|
end // end case sLd
|
|
|
|
sSt : begin
|
|
bitRamRw = 1; byteRamRw = 1; outputRw = 1;
|
|
state = s;
|
|
end
|
|
|
|
sAlu : begin
|
|
accEn = 1;
|
|
accMuxSel = `accMuxSelAluOut;
|
|
state = s;
|
|
end
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
sTc : begin
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
state = s;
|
|
end
|
|
`endif
|
|
|
|
`ifdef UART_peripheral
|
|
sUart : begin
|
|
uartRead = 0; uartWrite = 0;
|
|
state = s;
|
|
end
|
|
`endif
|
|
|
|
`ifdef SPI_peripheral
|
|
sSpi : begin
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
state = s;
|
|
end
|
|
`endif
|
|
|
|
default : begin
|
|
$write (" control unit FSM in unknown state. ");
|
|
end
|
|
endcase // end case (state)
|
|
end // end else part (outermost)
|
|
|
|
|
|
|
|
end // end always
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
