| Line 3... |
Line 3... |
`include "defines.v"
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`include "defines.v"
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module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
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module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
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branch,
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branch,
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accMuxSel, accEn, op2MuxSel, aluOpcode,
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accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,
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bitRamEn, bitRamRw, byteRamEn, byteRamRw,
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bitRamEn, bitRamRw, byteRamEn, byteRamRw,
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inputRead, outputRw
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inputRead, outputRw
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|
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
|
, entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn
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, entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn
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| Line 31... |
Line 31... |
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output branch;
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output branch;
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output [`accMuxSelLen-1:0] accMuxSel;
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output [`accMuxSelLen-1:0] accMuxSel;
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output accEn;
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output accEn;
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output [`op2MuxSelLen-1:0] op2MuxSel;
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output [`op2MuxSelLen-1:0] op2MuxSel;
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output aluEn;
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output [`aluOpcodeLen-1:0] aluOpcode;
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output [`aluOpcodeLen-1:0] aluOpcode;
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output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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output inputRead, outputRw;
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output inputRead, outputRw;
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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| Line 51... |
Line 52... |
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reg branch;
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reg branch;
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reg [`accMuxSelLen-1:0] accMuxSel;
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reg [`accMuxSelLen-1:0] accMuxSel;
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reg accEn;
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reg accEn;
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reg [`op2MuxSelLen-1:0] op2MuxSel;
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reg [`op2MuxSelLen-1:0] op2MuxSel;
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reg aluEn;
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reg [`aluOpcodeLen-1:0] aluOpcode;
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reg [`aluOpcodeLen-1:0] aluOpcode;
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reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
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reg inputRead, outputRw;
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reg inputRead, outputRw;
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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| Line 91... |
Line 93... |
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if (reset)
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if (reset)
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begin
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begin
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state = s;
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state = s;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluOpcode = 0; bitRamEn = 0;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluEn = 0; aluOpcode = 0; bitRamEn = 0;
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bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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`ifdef timeAndCounter_peripheral
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`endif
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| Line 127... |
Line 129... |
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branch = 1; // branch to some address . . .
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branch = 1; // branch to some address . . .
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accMuxSel = 0;
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accMuxSel = 0;
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accEn = 0;
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accEn = 0;
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op2MuxSel = 0;
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op2MuxSel = 0;
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aluEn = 0;
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aluOpcode = 0;
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aluOpcode = 0;
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bitRamEn = 0;
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bitRamEn = 0;
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bitRamRw = 1;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamEn = 0;
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byteRamRw = 1;
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byteRamRw = 1;
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| Line 156... |
Line 159... |
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`JMP : begin
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`JMP : begin
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state = sBr;
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state = sBr;
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if (acc0)
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branch = 1; // branch to some address . . .
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branch = 1; // branch to some address . . .
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else
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branch = 0;
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accMuxSel = 0;
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accMuxSel = 0;
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accEn = 0;
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accEn = 0;
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op2MuxSel = 0;
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op2MuxSel = 0;
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aluEn = 0;
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aluOpcode = 0;
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aluOpcode = 0;
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bitRamEn = 0;
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bitRamEn = 0;
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bitRamRw = 1;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamEn = 0;
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byteRamRw = 1;
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byteRamRw = 1;
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| Line 199... |
Line 206... |
2'b01 : op2MuxSel = `op2MuxSelOutput;
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2'b01 : op2MuxSel = `op2MuxSelOutput;
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2'b10 : op2MuxSel = `op2MuxSelBitRam;
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2'b10 : op2MuxSel = `op2MuxSelBitRam;
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2'b11 : op2MuxSel = `op2MuxSelByteRam;
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2'b11 : op2MuxSel = `op2MuxSelByteRam;
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default: op2MuxSel = `op2MuxSelInput;
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default: op2MuxSel = `op2MuxSelInput;
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endcase
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endcase
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aluEn = 1;
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aluOpcode = `LD_data;
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aluOpcode = `LD_data;
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bitRamEn = 0;
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bitRamEn = 1;
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bitRamRw = 1;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamEn = 1;
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byteRamRw = 1;
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byteRamRw = 1;
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inputRead = 0;
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inputRead = 1;
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outputRw = 1;
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outputRw = 1;
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`ifdef timeAndCounter_peripheral
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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`endif
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`endif
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| Line 234... |
Line 241... |
branch = 0;
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branch = 0;
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accMuxSel = `accMuxSelImmData; // select imm data thr mux
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accMuxSel = `accMuxSelImmData; // select imm data thr mux
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accEn = 1; // acc enabled
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accEn = 1; // acc enabled
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op2MuxSel = 0;
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op2MuxSel = 0;
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aluOpcode = 0;
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aluOpcode = 0;
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aluEn = 0;
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bitRamEn = 0;
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bitRamEn = 0;
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bitRamRw = 1;
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bitRamRw = 1;
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byteRamEn = 0;
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byteRamEn = 0;
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byteRamRw = 1;
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byteRamRw = 1;
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inputRead = 0;
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inputRead = 0;
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| Line 264... |
Line 272... |
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branch = 0;
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branch = 0;
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accMuxSel = 0;
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accMuxSel = 0;
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accEn = 0;
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accEn = 0;
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op2MuxSel = 0;
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op2MuxSel = 0;
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aluEn = 0;
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aluOpcode = 0;
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aluOpcode = 0;
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bitRamRw = 0;
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byteRamRw = 0;
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inputRead = 0;
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inputRead = 0;
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case (iomemCode)
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case (iomemCode)
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2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; end
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2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
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2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; end
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2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
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2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
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2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
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default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
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default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
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endcase
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endcase
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`ifdef timeAndCounter_peripheral
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`ifdef timeAndCounter_peripheral
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| Line 295... |
Line 302... |
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`ADD : begin
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`ADD : begin
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state = sAlu;
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state = sAlu;
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aluOpcode = `ADD_alu;
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aluOpcode = `ADD_alu;
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aluEn = 1;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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|
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`ifdef timeAndCounter_peripheral
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`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 317... |
Line 324... |
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`SUB : begin
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`SUB : begin
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state = sAlu;
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state = sAlu;
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aluOpcode = `SUB_alu;
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aluOpcode = `SUB_alu;
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aluEn = 1;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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|
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`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 342... |
Line 349... |
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`AND : begin
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`AND : begin
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state = sAlu;
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state = sAlu;
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aluOpcode = `AND_alu;
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aluOpcode = `AND_alu;
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aluEn = 1;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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|
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`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 365... |
Line 372... |
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`OR : begin
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`OR : begin
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state = sAlu;
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state = sAlu;
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aluOpcode = `OR_alu;
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aluOpcode = `OR_alu;
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aluEn = 1;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 388... |
Line 395... |
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`XOR : begin
|
`XOR : begin
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state = sAlu;
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state = sAlu;
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aluOpcode = `XOR_alu;
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aluOpcode = `XOR_alu;
|
|
aluEn = 1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
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bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 411... |
Line 418... |
|
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|
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`GrT : begin
|
`GrT : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `GT_alu;
|
aluOpcode = `GT_alu;
|
|
aluEn = 1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 436... |
Line 443... |
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|
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`GE : begin
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`GE : begin
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state = sAlu;
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state = sAlu;
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aluOpcode = `GE_alu;
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aluOpcode = `GE_alu;
|
|
aluEn = 1;
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branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 461... |
Line 468... |
|
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|
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`EQ : begin
|
`EQ : begin
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state = sAlu;
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state = sAlu;
|
aluOpcode = `EQ_alu;
|
aluOpcode = `EQ_alu;
|
|
aluEn = 1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
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| Line 486... |
Line 493... |
|
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|
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`LE : begin
|
`LE : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `LE_alu;
|
aluOpcode = `LE_alu;
|
|
aluEn = 1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
| Line 511... |
Line 518... |
|
|
|
|
`LT : begin
|
`LT : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `LT_alu;
|
aluOpcode = `LT_alu;
|
|
aluEn = 1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
| Line 537... |
Line 544... |
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 0; uartWrite = 0;
|
| Line 559... |
Line 566... |
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 0; uartWrite = 0;
|
| Line 582... |
Line 589... |
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 0; uartWrite = 0;
|
| Line 606... |
Line 613... |
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;
|
|
|
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
|
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
|
|
|
aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 0; uartWrite = 0;
|
| Line 630... |
Line 637... |
|
|
entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
|
|
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
|
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
|
|
|
aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 0; uartWrite = 0;
|
| Line 655... |
Line 662... |
|
|
uartRead = 1; uartWrite = 0;
|
uartRead = 1; uartWrite = 0;
|
|
|
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
|
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
|
|
|
aluOpcode = 0; branch = 0;op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0;op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
`endif
|
`endif
|
| Line 678... |
Line 685... |
`UARTwr : begin
|
`UARTwr : begin
|
state = sUart;
|
state = sUart;
|
|
|
uartRead = 0; uartWrite = 1;
|
uartRead = 0; uartWrite = 1;
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
`endif
|
`endif
|
| Line 702... |
Line 709... |
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
`endif
|
`endif
|
| Line 725... |
Line 732... |
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
`endif
|
`endif
|
| Line 748... |
Line 755... |
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
`endif
|
`endif
|
| Line 771... |
Line 778... |
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
|
|
|
|
|
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
`endif
|
`endif
|
| Line 804... |
Line 811... |
state = s;
|
state = s;
|
end // end case sBr
|
end // end case sBr
|
|
|
|
|
sLd : begin
|
sLd : begin
|
accEn = 0;
|
aluEn = 0;
|
|
accEn = 1;
|
|
accMuxSel = `accMuxSelAluOut;
|
state = s;
|
state = s;
|
end // end case sLd
|
end // end case sLd
|
|
|
sSt : begin
|
sSt : begin
|
bitRamRw = 1; byteRamRw = 1; outputRw = 1;
|
bitRamRw = 1; byteRamRw = 1; outputRw = 1;
|
state = s;
|
state = s;
|
end
|
end
|
|
|
sAlu : begin
|
sAlu : begin
|
|
aluEn = 0;
|
accEn = 1;
|
accEn = 1;
|
accMuxSel = `accMuxSelAluOut;
|
accMuxSel = `accMuxSelAluOut;
|
state = s;
|
state = s;
|
end
|
end
|
|
|
