| Line 206... |
Line 206... |
2'b01 : op2MuxSel = `op2MuxSelOutput;
|
2'b01 : op2MuxSel = `op2MuxSelOutput;
|
2'b10 : op2MuxSel = `op2MuxSelBitRam;
|
2'b10 : op2MuxSel = `op2MuxSelBitRam;
|
2'b11 : op2MuxSel = `op2MuxSelByteRam;
|
2'b11 : op2MuxSel = `op2MuxSelByteRam;
|
default: op2MuxSel = `op2MuxSelInput;
|
default: op2MuxSel = `op2MuxSelInput;
|
endcase
|
endcase
|
aluEn = 1;
|
aluEn = 1'b1;
|
aluOpcode = `LD_data;
|
aluOpcode = `LD_data;
|
|
|
bitRamEn = 1;
|
bitRamEn = 1'b1;
|
bitRamRw = 1;
|
bitRamRw = 1'b1;
|
byteRamEn = 1;
|
byteRamEn = 1'b1;
|
byteRamRw = 1;
|
byteRamRw = 1'b1;
|
inputRead = 1;
|
inputRead = 1'b1;
|
outputRw = 1;
|
outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end // end case Ld
|
end // end case Ld
|
|
|
|
|
|
|
|
|
`Ldi : begin
|
`Ldi : begin
|
state = sAlu;
|
state = sAlu;
|
|
|
branch = 0;
|
branch = 1'b0;
|
accMuxSel = `accMuxSelImmData; // select imm data thr mux
|
accMuxSel = `accMuxSelImmData; // select imm data thr mux
|
accEn = 1; // acc enabled
|
accEn = 1'b1; // acc enabled
|
op2MuxSel = 0;
|
op2MuxSel = 1'b0;
|
aluOpcode = 0;
|
aluOpcode = 1'b0;
|
aluEn = 0;
|
aluEn = 1'b0;
|
bitRamEn = 0;
|
bitRamEn = 1'b0;
|
bitRamRw = 1;
|
bitRamRw = 1'b1;
|
byteRamEn = 0;
|
byteRamEn = 1'b0;
|
byteRamRw = 1;
|
byteRamRw = 1'b1;
|
inputRead = 0;
|
inputRead = 1'b0;
|
outputRw = 1;
|
outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end // end case Ldi
|
end // end case Ldi
|
|
|
|
|
|
|
`ST : begin
|
`ST : begin
|
state = sSt;
|
state = sSt;
|
|
|
branch = 0;
|
branch = 1'b0;
|
accMuxSel = 0;
|
accMuxSel = 1'b0;
|
accEn = 0;
|
accEn = 1'b0;
|
op2MuxSel = 0;
|
op2MuxSel = 1'b0;
|
aluEn = 0;
|
aluEn = 1'b0;
|
aluOpcode = 0;
|
aluOpcode = 1'b0;
|
inputRead = 0;
|
inputRead = 1'b0;
|
|
|
case (iomemCode)
|
case (iomemCode)
|
2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
|
2'b01 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end
|
2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
|
2'b10 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end
|
2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
|
2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end
|
default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
|
default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end
|
endcase
|
endcase
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
|
|
`ADD : begin
|
`ADD : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `ADD_alu;
|
aluOpcode = `ADD_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
`SUB : begin
|
`SUB : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `SUB_alu;
|
aluOpcode = `SUB_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
// MUL & DIV are not implemented
|
// MUL & DIV are not implemented
|
| Line 349... |
Line 349... |
|
|
|
|
`AND : begin
|
`AND : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `AND_alu;
|
aluOpcode = `AND_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
|
|
`OR : begin
|
`OR : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `OR_alu;
|
aluOpcode = `OR_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
|
|
`XOR : begin
|
`XOR : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `XOR_alu;
|
aluOpcode = `XOR_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
|
|
`GrT : begin
|
`GrT : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `GT_alu;
|
aluOpcode = `GT_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
| Line 443... |
Line 443... |
|
|
|
|
`GE : begin
|
`GE : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `GE_alu;
|
aluOpcode = `GE_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
| Line 468... |
Line 468... |
|
|
|
|
`EQ : begin
|
`EQ : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `EQ_alu;
|
aluOpcode = `EQ_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
| Line 493... |
Line 493... |
|
|
|
|
`LE : begin
|
`LE : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `LE_alu;
|
aluOpcode = `LE_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
| Line 518... |
Line 518... |
|
|
|
|
`LT : begin
|
`LT : begin
|
state = sAlu;
|
state = sAlu;
|
aluOpcode = `LT_alu;
|
aluOpcode = `LT_alu;
|
aluEn = 1;
|
aluEn = 1'b1;
|
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
`PRE : begin
|
`PRE : begin
|
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b1; tcLoadEn = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
`ETY : begin
|
`ETY : begin
|
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b1; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
`RST : begin
|
`RST : begin
|
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b1; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
`LdTC : begin
|
`LdTC : begin
|
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b1;
|
|
|
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
|
accMuxSel = `accMuxSelTcLoad; accEn = 1'b1; // loading TC status data
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
|
|
`ifdef timeAndCounter_peripheral
|
`ifdef timeAndCounter_peripheral
|
`LdACC : begin
|
`LdACC : begin
|
state = sTc;
|
state = sTc;
|
|
|
entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b1; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
|
|
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
|
accMuxSel = `accMuxSelTcAcc; accEn = 1'b1; // loading TC ACC data
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
| Line 658... |
Line 658... |
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
`UARTrd : begin
|
`UARTrd : begin
|
state = sUart;
|
state = sUart;
|
|
|
uartRead = 1; uartWrite = 0;
|
uartRead = 1'b1; uartWrite = 1'b0;
|
|
|
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
|
accMuxSel = `accMuxSelUartData; accEn = 1'b1; // loading UART data
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0;op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
|
`endif
|
|
end
|
|
`endif
|
|
|
|
|
|
|
|
`ifdef UART_peripheral
|
|
`UARTstat : begin
|
|
state = sUart;
|
|
|
|
uartRead = 1'b0; uartWrite = 1'b0;
|
|
|
|
accMuxSel = `accMuxSelUartStat; accEn = 1'b1; // loading UART status
|
|
|
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
|
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
|
`ifdef timerAndCounter_peripheral
|
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
|
`endif
|
|
|
|
|
|
`ifdef SPI_peripheral
|
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
| Line 683... |
Line 707... |
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
`UARTwr : begin
|
`UARTwr : begin
|
state = sUart;
|
state = sUart;
|
|
|
uartRead = 0; uartWrite = 1;
|
uartRead = 1'b0; uartWrite = 1'b1;
|
|
|
aluEn = 0; aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
`endif
|
`endif
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
| Line 706... |
Line 730... |
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
`SPIxFER : begin
|
`SPIxFER : begin
|
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b1; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
`endif
|
`endif
|
|
|
| Line 729... |
Line 753... |
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
`SPIstat : begin
|
`SPIstat : begin
|
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b1; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
`endif
|
`endif
|
|
|
| Line 752... |
Line 776... |
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
`SPIwBUF : begin
|
`SPIwBUF : begin
|
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b1; spiBufShift = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
`endif
|
`endif
|
|
|
| Line 775... |
Line 799... |
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
`SPIrBUF : begin
|
`SPIrBUF : begin
|
state = sSpi;
|
state = sSpi;
|
|
|
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b1; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
|
|
|
|
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
|
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
|
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
|
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
`endif
|
`endif
|
|
|
end
|
end
|
`endif
|
`endif
|
|
|
| Line 805... |
Line 829... |
|
|
end // end case (s)
|
end // end case (s)
|
|
|
|
|
sBr : begin
|
sBr : begin
|
branch = 0;
|
branch = 1'b0;
|
state = s;
|
state = s;
|
end // end case sBr
|
end // end case sBr
|
|
|
|
|
sLd : begin
|
sLd : begin
|
aluEn = 0;
|
aluEn = 1'b0;
|
accEn = 1;
|
accEn = 1'b1;
|
accMuxSel = `accMuxSelAluOut;
|
accMuxSel = `accMuxSelAluOut;
|
state = s;
|
state = s;
|
end // end case sLd
|
end // end case sLd
|
|
|
sSt : begin
|
sSt : begin
|
bitRamRw = 1; byteRamRw = 1; outputRw = 1;
|
bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1;
|
state = s;
|
state = s;
|
end
|
end
|
|
|
sAlu : begin
|
sAlu : begin
|
aluEn = 0;
|
aluEn = 1'b0;
|
accEn = 1;
|
accEn = 1'b1;
|
accMuxSel = `accMuxSelAluOut;
|
accMuxSel = `accMuxSelAluOut;
|
state = s;
|
state = s;
|
end
|
end
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
sTc : begin
|
sTc : begin
|
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
|
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
|
state = s;
|
state = s;
|
end
|
end
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
sUart : begin
|
sUart : begin
|
uartRead = 0; uartWrite = 0;
|
uartRead = 1'b0; uartWrite = 1'b0;
|
state = s;
|
state = s;
|
end
|
end
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
`ifdef SPI_peripheral
|
sSpi : begin
|
sSpi : begin
|
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
|
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
|
state = s;
|
state = s;
|
end
|
end
|
`endif
|
`endif
|
|
|
default : begin
|
default : begin
|
