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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [controlUnit.v] - Diff between revs 8 and 9

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Rev 8	Rev 9
Line 193...	Line 193...



`Ld : begin	`Ld : begin
`// load thr. op2 MUX and alu.... enable acc in next cycle`	`// load thr. op2 MUX and alu.... enable acc in next cycle`
`state = sLd;`	`state = sAlu;`

`branch = 0;`	`branch = 0;`
	// accMuxSel = `accMuxSelAluOut;
`accMuxSel = 0;`	`accMuxSel = 0;`
`accEn = 0;`	`accEn = 0;`

`case (iomemCode)`	`case (iomemCode)`
2'b00 : op2MuxSel = `op2MuxSelInput;	2'b00 : op2MuxSel = `op2MuxSelInput;
Line 234...	Line 235...




`Ldi : begin	`Ldi : begin
`state = sAlu;`	`state = sLd;`

`branch = 1'b0;`	`branch = 1'b0;`
accMuxSel = `accMuxSelImmData; // select imm data thr mux	accMuxSel = `accMuxSelImmData; // select imm data thr mux
`accEn = 1'b1; // acc enabled`	`accEn = 1'b1; // acc enabled`
`op2MuxSel = 1'b0;`	`op2MuxSel = 1'b0;`
Line 277...	Line 278...
`aluEn = 1'b0;`	`aluEn = 1'b0;`
`aluOpcode = 1'b0;`	`aluOpcode = 1'b0;`
`inputRead = 1'b0;`	`inputRead = 1'b0;`

`case (iomemCode)`	`case (iomemCode)`
`2'b01 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`	`2'b10 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`
`2'b10 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`	`2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end`
`2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end`	`2'b01 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end`
`default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end`	`default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end`
`endcase`	`endcase`

`ifdef timeAndCounter_peripheral	`ifdef timeAndCounter_peripheral
`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`	`entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;`
Line 818...	Line 819...
`end`	`end`
`endif	`endif

`default : begin`	`default : begin`

`$write ("\nunknown/unused instruction op-code encountered by control unit ");`	`$write ("\n", $time, "ns unknown/unused instruction op-code encountered by control unit");`
`// $stop;`	`// $stop;`
`end`	`end`
`endcase // end case (instOpCode)`	`endcase // end case (instOpCode)`


Line 835...	Line 836...
`state = s;`	`state = s;`
`end // end case sBr`	`end // end case sBr`


`sLd : begin`	`sLd : begin`
`aluEn = 1'b0;`	`accEn = 1'b0;`
`accEn = 1'b1;`
accMuxSel = `accMuxSelAluOut;
`state = s;`	`state = s;`
`end // end case sLd`	`end // end case sLd`

`sSt : begin`	`sSt : begin`
`bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1;`	`bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1;`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [controlUnit.v] - Diff between revs 8 and 9