OpenCores
URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [defines.v] - Diff between revs 6 and 7

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 6 Rev 7
Line 2... Line 2...
// 16-bit process controller defines
// 16-bit process controller defines
 
 
`define         immDataLen                      8
`define         immDataLen                      8
 
 
// program counter & instruction register
// program counter & instruction register
 
`define         instAddrLen                     10                      // 10-bit address => 1024 inst in rom
`define         instLen                         15                      // 15-bit fixed-length instructions
`define         instLen                         15                      // 15-bit fixed-length instructions
`define         instOpCodeLen           5
`define         instOpCodeLen           5
`define         instFieldLen            10
`define         instFieldLen            10
 
 
 
 
Line 33... Line 34...
`define         RST                                     `instOpCodeLen'b10011
`define         RST                                     `instOpCodeLen'b10011
`define         LdTC                                    `instOpCodeLen'b10100
`define         LdTC                                    `instOpCodeLen'b10100
`define         LdACC                                   `instOpCodeLen'b10101
`define         LdACC                                   `instOpCodeLen'b10101
`define         UARTrd                          `instOpCodeLen'b10110
`define         UARTrd                          `instOpCodeLen'b10110
`define         UARTwr                          `instOpCodeLen'b10111
`define         UARTwr                          `instOpCodeLen'b10111
`define         SPIxFER                         `instOpCodeLen'b11000
`define         UARTstat                                `instOpCodeLen'b11000
`define         SPIstat                         `instOpCodeLen'b11001
`define         SPIxFER                         `instOpCodeLen'b11001
`define         SPIwBUF                         `instOpCodeLen'b11010
`define         SPIstat                         `instOpCodeLen'b11010
`define         SPIrBUF                         `instOpCodeLen'b11011
`define         SPIwBUF                         `instOpCodeLen'b11011
 
`define         SPIrBUF                         `instOpCodeLen'b11100
 
 
// alu opcodes
// alu opcodes
`define         aluOpcodeLen            4
`define         aluOpcodeLen            4
`define         AND_alu                         `aluOpcodeLen'b0
`define         AND_alu                         `aluOpcodeLen'b0
`define         OR_alu                          `aluOpcodeLen'b1
`define         OR_alu                          `aluOpcodeLen'b1
Line 77... Line 79...
`define         accMuxSelLen                    4               // 2^4 = 16 selections available for accumulator
`define         accMuxSelLen                    4               // 2^4 = 16 selections available for accumulator
`define         accMuxSelImmData                `accMuxSelLen'b0
`define         accMuxSelImmData                `accMuxSelLen'b0
`define         accMuxSelAluOut         `accMuxSelLen'b1
`define         accMuxSelAluOut         `accMuxSelLen'b1
`define         accMuxSelTcLoad         `accMuxSelLen'b10
`define         accMuxSelTcLoad         `accMuxSelLen'b10
`define         accMuxSelTcAcc                  `accMuxSelLen'b11
`define         accMuxSelTcAcc                  `accMuxSelLen'b11
`define         accMuxSelUart                   `accMuxSelLen'b100
`define         accMuxSelUartData               `accMuxSelLen'b100
`define         accMuxSelSpiStat                `accMuxSelLen'b101
`define         accMuxSelUartStat               `accMuxSelLen'b101
`define         accMuxSelSpiBuf         `accMuxSelLen'b110
`define         accMuxSelSpiStat                `accMuxSelLen'b110
 
`define         accMuxSelSpiBuf         `accMuxSelLen'b111
 
 
// operand2 multiplexer
// operand2 multiplexer
`define         op2MuxSelLen                    4               // 2^4 = 16 selections available for op2
`define         op2MuxSelLen                    4               // 2^4 = 16 selections available for op2
`define         op2MuxSelInput                  `op2MuxSelLen'b0
`define         op2MuxSelInput                  `op2MuxSelLen'b0
`define         op2MuxSelOutput         `op2MuxSelLen'b1
`define         op2MuxSelOutput         `op2MuxSelLen'b1
Line 106... Line 109...
// Timer-Counter
// Timer-Counter
`define         tcAccLen                                8               // 8-bit accumulated value
`define         tcAccLen                                8               // 8-bit accumulated value
`define         tcPresetLen                     8               // 8-bit preset value
`define         tcPresetLen                     8               // 8-bit preset value
`define         tcAddrLen                       4
`define         tcAddrLen                       4
`define         tcTypeLen                       2               // max 4-types
`define         tcTypeLen                       2               // max 4-types
`define         tcNumbers                       16              // total 16 modules (8-timers, 8-counters)
`define         tcNumbers                       8               // total 8 modules (4-timers, 4-counters)
 
 
`define         timerType1                      `tcTypeLen'b0
`define         timerType1                      `tcTypeLen'b0
`define         timerType2                      `tcTypeLen'b1
`define         timerType2                      `tcTypeLen'b1
`define         timerType3                      `tcTypeLen'b10
`define         timerType3                      `tcTypeLen'b10
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.