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https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module inputRegister (reset, inputs, inputRead, inputReadAddr, inputReadOut);
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module inputRegister (inputs, inputReadAddr, inputReadOut);
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input [`inputNumber-1:0] inputs;
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input [`inputNumber-1:0] inputs;
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input inputRead, reset;
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input [`inputAddrLen-1:0] inputReadAddr;
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input [`inputAddrLen-1:0] inputReadAddr;
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output inputReadOut;
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output inputReadOut;
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reg inputReadOut;
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wire [`inputNumber-1:0] inputs;
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reg [`inputNumber-1:0] inputReg;
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always @ (reset or inputs or inputRead or inputReadAddr)
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begin
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if (reset)
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assign inputReadOut = inputs[inputReadAddr];
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begin
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inputReadOut = 1'bz;
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$write ("\nmodule inputRegister is reset ");
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end
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else
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begin
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inputReg = inputs;
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if (inputRead)
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begin
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inputReadOut = inputReg [inputReadAddr];
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$write ("\nreading input : module inputRegister ");
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end
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end
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end
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endmodule
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endmodule
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