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https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
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Rev 12 |
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Line 47... |
input reset, outputRw;
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input reset, outputRw;
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input [`outputAddrLen-1:0] outputRwAddr;
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input [`outputAddrLen-1:0] outputRwAddr;
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input outputWriteIn;
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input outputWriteIn;
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output outputReadOut;
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output outputReadOut;
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output [`outputNumber-1:0] outputs;
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output wire [`outputNumber-1:0] outputs;
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reg outputReadOut;
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reg outputReadOut;
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reg [`outputNumber-1:0] outputs = 0;
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// reg [`outputNumber-1:0] outputs = 0;
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reg [`outputNumber-1 :0] outputReg = 0;
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reg [`outputNumber-1 :0] outputReg = 0;
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always @ (reset or outputRw or outputRwAddr or outputWriteIn or outputReg)
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always @ (reset or outputRw or outputRwAddr or outputWriteIn or outputReg)
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| Line 67... |
Line 67... |
end
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end
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else
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else
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begin
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begin
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outputs = outputReg;
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if (outputRw) // read output status
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if (outputRw) // read output status
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begin
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begin
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outputReadOut = outputReg[outputRwAddr];
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outputReadOut = outputReg[outputRwAddr];
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// $write ("\nreading output register : module outputRegister ");
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// $write ("\nreading output register : module outputRegister ");
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end
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end
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else // write operation
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else // write operation
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begin
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begin
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outputReg[outputRwAddr] = outputWriteIn;
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outputReg[outputRwAddr] = outputWriteIn;
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// $write ("\nwriting to the output register : module outputRegister ");
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$write ("\nwriting to the output register : module outputRegister ");
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end
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end
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end
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end
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end
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end
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assign outputs = outputReg;
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endmodule
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endmodule
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