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https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
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input clk, reset, branch;
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input clk, reset, branch;
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input [`instAddrLen-1:0] pcIn;
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input [`instAddrLen-1:0] pcIn;
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output [`instAddrLen-1:0] pcOut;
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output [`instAddrLen-1:0] pcOut;
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reg [`instAddrLen-1:0] pc = `instAddrLen'b0;
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reg [`instAddrLen-1:0] pcOut = `instAddrLen'b0;
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always @ (posedge clk or posedge reset)
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always @ (posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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pc = `instAddrLen'b0;
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pcOut = `instAddrLen'b0;
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$write ("\nprogram counter module is reset. Starting at address 00h ");
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$write ("\nprogram counter module is reset. Starting at address 00h ");
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end
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end
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else
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else
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begin
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begin
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if(branch)
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if(branch)
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begin
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begin
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pc = pcIn;
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pcOut = pcIn;
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$write ("\nbranching at address %h", pcIn);
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$write ("\nbranching at address %h", pcIn);
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end
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end
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else
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else
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begin
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begin
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pc = pc + 1'b1;
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pcOut = pcOut + 1'b1;
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end
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end
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end
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end
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end // end always
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end // end always
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assign pcOut = pc;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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